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SP6120 Datasheet(PDF) 12 Page - Sipex Corporation |
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SP6120 Datasheet(HTML) 12 Page - Sipex Corporation |
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12 / 13 page  12 Date: 5/25/04 SP6120 Low Voltage, AnyFETTM, Synchronous, Buck Controller © Copyright 2004 Sipex Corporation 0V MAX DC Load Current MIN 0A Output Voltage VOUT Reset Set V(VCC) Main Loop 3% High Latch On 0V V(VCC) 3% Low Latch On . TIME The NFET/PFET programmability is for the high side MOSFET. When designing DC/DC converters, it is not always obvious when to use an NFET with a charge pump or a simple PFET for the high side MOSFET. Often, the controller has to be changed, making performance evalu- ations difficult. This difficulty is worsened by the limited availability of true low voltage con- trollers. In addition, by also programming the mode, continuous or discontinuous, switch mode power designs that are successful in bus applica- tions can now find homes in portable applica- tions. Secondary Loop (3% Window Comparator) DSP, microcontroller and microprocessor ap- plications have very strict supply voltage re- quirements. In addition, the current require- ments to these devices can change drastically. Linear regulators, typically the workhorse for DC/DC step-down, do a great job managing accuracy and transient response at the expense of efficiency. On the other hand, PWM switch- ing regulators typically do a great job managing efficiency at the expense of output ripple and line/load step response. The trick in PWM controller design is to emulate the transient response of the linear regulator. Of course improving transient response should be transparent to the power supply designer. Very often this is not the case. Usually the very circuitry that improves the controllers transient response adversely interferes with the main PWM loop or complicates the board level de- sign of the power converter. The SP6120 handles line/load transient response in a new way. First, a window comparator detects whether the output voltage is above or below the regulated value by 3%. Then, a proprietary “Ripple & Frequency Independent” algorithm synchronizes the output of the win- dow comparator with the peak and valley of the inductor current waveform. 3% low detection is synchronized with inductor current peak; 3% high detection is synchronized with the inductor current valley. However, in order to eliminate Secondary Loop (continued) any additional loops, the current peak and val- ley are determined by the edges associated with the on-time in the main loop. The set pulse corresponding to the start of an on-time indi- cates a current valley and the reset pulse corre- sponding to the end of an on-time indicates a current peak. In effect, the main loop deter- mines the status of the secondary loop. Notice that the output voltage appears to coast toward the regulated value during periods where the main loop would be telling the drivers to THEORY OF OPERATIONS: Continued |
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