MCM69F735 datasheet(12/16 Pages) MOTOROLA | 128K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

Part #	MCM69F735

Description	128K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

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Manufacturer	MOTOROLA [Motorola, Inc]

Direct Link	http://www.freescale.com

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MCM69F735

12

MOTOROLA FAST SRAM

APPLICATION INFORMATION

STOP CLOCK OPERATION

In the stop clock mode of operation, the SRAM will hold all

state and data values even though the clock is not running

(full static operation). The SRAM design allows the clock to

start with ADSP and ADSC, and stops the clock after the last

write data is latched, or the last read data is driven out.

When starting and stopping the clock, the AC clock timing

and parametrics must be strictly maintained. For example,

clock pulse width and edge rates must be guaranteed when

starting and stopping the clocks.

To achieve the lowest power operation for all three stop

clock modes, stop read, stop write, and stop deselect:

1. Force the clock to a low state.

2. Force the control signals to an inactive state (this guar-

antees any potential source of noise on the clock input

will not start an unplanned on activity).

3. Force the address inputs to a low state (VIL), preferably

< 0.2 V.

K

ADSP

ADDRESS

ADV

A1

A2

Q(A2)

Q(A2+1)

Q(A1)

ADSP

(INITIATES

BURST READ)

CLOCK STOP

(CONTINUE

BURST READ)

WAKE UP ADSP

(INITIATES BURST READ)

DQx

NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).

Best results are obtained if VIL < 0.2 V.

STOP CLOCK WITH READ TIMING

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