MCM6929A

4

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to +70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . .

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

2 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . .

Output Load

See Figure 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6929A–8

6929A–10

6929A–12

6929A–15

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

8

—

10

—

12

—

15

—

ns

3

Address Access Time

tAVQV

—

8

—

10

—

12

—

15

ns

Enable Access Time

tELQV

—

8

—

10

—

12

—

15

ns

Output Enable Access Time

tGLQV

—

4

—

5

—

6

—

7

ns

Output Hold from Address Change

tAXQX

3

—

3

—

3

—

3

—

ns

Enable Low to Output Active

tELQX

3

—

3

—

3

—

3

—

ns

4,5,6

Output Enable Low to Output Active

tGLQX

0

—

0

—

0

—

0

—

ns

4,5,6

Enable High to Output High–Z

tEHQZ

—

4

—

5

—

6

—

7

ns

4,5,6

Output Enable High to Output High–Z

tGHQZ

—

4

—

5

—

6

—

7

ns

4,5,6

NOTES:

1. W is high for read cycle.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from

device to device.

5. Transition is measured 200 mV from steady–state voltage.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E = VIL, G = VIL).

8. Addresses valid prior to or coincident with E going low.

The table of timing values shows either a minimum

or a maximum limit for each parameter. Input require-

ments are specified from the external system point of

view. Thus, address setup time is shown as a mini-

mum since the system must supply at least that much

time. On the other hand, responses from the memory

are specified from the device point of view. Thus, the

access time is shown as a maximum since the device

never provides data later than that time.

TIMING LIMITS

OUTPUT

Z0 = 50 Ω

RL = 50 Ω

VL = 1.5 V

Figure 1. AC Test Load