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56F84442VLH Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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56F84442VLH Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 67 page  Table 1. 56F844x/5x/7x Family (continued) Part Number MC56F84 789 786 769 766 763 553 550 543 540 587 585 567 565 462 452 451 442 441 Standard channels 4 1 4 1 1 1 0 1 0 2x 12 1x 12, 1x9 2x 12 1x 12, 1x9 1x9 1x9 1x6 1x9 1x6 PWMB with input capture: Standard channels 1x 12 1x7 1x 12 1x7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 Quad Decoder 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 DMA Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes CMP 4 4 4 4 4 4 3 4 3 4 4 4 4 4 4 3 4 3 QSCI 3 3 3 3 2 2 2 2 2 3 3 3 3 2 2 2 2 2 QSPI 3 2 3 2 2 2 2 2 2 3 2 3 2 2 2 2 2 2 I2C/SMBus 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 FlexCAN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 LQFP package pin count 100 80 100 80 64 64 48 64 48 100 80 100 80 64 64 48 64 48 1. This total assumes no FlexNVM is used with FlexRAM for EEPROM. 1.2 56800EX 32-bit Digital Signal Controller Core • Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual Harvard architecture • Three internal address buses • Four internal data buses: two 32-bit primary buses, one 16-bit secondary data bus, and one 16-bit instruction bus • 32-bit data accesses • Support for concurrent instruction fetches in the same cycle and dual data accesses in the same cycle • 20 addressing modes • As many as 60 million instructions per second (MIPS) at 60 MHz core frequency • 162 basic instructions • Instruction set supports both fractional arithmetic and integer arithmetic • 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical operation • Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator (MAC) with dual parallel moves Overview MC56F844xx Advance Information Data Sheet, Rev. 2, 06/2012. Freescale Semiconductor, Inc. Preliminary 5 General Business Information |
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