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EN39SL800 Datasheet(PDF) 9 Page - Eon Silicon Solution Inc.

Part No. EN39SL800
Description  8 Megabit (512K x 16-bit) Flash Memory With 4Kbytes Uniform Sector, CMOS 1.8 Volt-only
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw
Logo EON - Eon Silicon Solution Inc.

EN39SL800 Datasheet(HTML) 9 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
or modifications due to changes in technical specifications.
Rev. H, Issue Date: 2011/02/14
Standby Mode
The EN39SL800 has a CMOS-compatible standby mode, which reduces the current to
< 0.2µA (typical). It
is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.2. When in standby modes, the
outputs are in a high-impedance state independent of the OE# input.
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within
erase-suspended sectors/blocks, the device outputs status data. After completing a programming operation
in the Erase Suspend mode, the system may once again read array data with the same exception. See
“Erase Suspend/Erase Resume Commands” for more additional information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” additional details.
Output Disable Mode
When the OE# pin is at a logic high level (VIH), the output from the EN39SL800 is disabled. The output
pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and block protection verification,
through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment
to automatically match a device to be programmed with its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID ( 9.0 V to 11.0 V) on address pin
A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when
verifying block protection, the block address must appear on the appropriate highest order address bits.
Refer to the corresponding block Address Tables. The Command Definitions table shows the remaining
address bits that are don’t-care. When all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on DQ15–DQ0.
To access the autoselect codes in-system; the host system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
“Command Definitions” for details on using the autoselect mode.
Write Mode
Write operations, including programming data and erasing sectors/blocks of memory, require the host
system to write a command or command sequence to the device. Write cycles are initiated by placing the
word address on the device’s address inputs while the data to be written is input on DQ [15:0] in Word
Mode. The host system must drive the CE# and WE# pins Low and the OE# pin High for a valid write
operation to take place. All addresses are latched on the falling edge of WE# and CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The system is not
required to provide further controls or timings. The device automatically provides internally generated
program / erase pulses and verifies the programmed /erased cells’ margin. The host system can detect

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