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EN39SL800 Datasheet(PDF) 17 Page - Eon Silicon Solution Inc.
EON [Eon Silicon Solution Inc.]
EN39SL800 Datasheet(HTML) 17 Page - Eon Silicon Solution Inc.
/ 45 page
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
or modifications due to changes in technical specifications.
Rev. H, Issue Date: 2011/02/14
WRITE OPERATION STATUS
DQ7: DATA# Polling
The EN39SL800 provides DATA# polling on DQ7 to indicate the status of the embedded operations. The
DATA# Polling feature is active during the embedded Programming, Sector/Block Erase, Chip Erase, and
Erase Suspend. (See Table 6)
When the embedded Programming is in progress, an attempt to read the device will produce the
complement of the data last written to DQ7. Upon the completion of the embedded Programming, an
attempt to read the device will produce the true data written to DQ7. For the embedded Programming,
DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7
output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output
during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE# or
CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of the WE# or CE#
pulse for chip erase or sector/block erase.
DATA# Polling must be performed at any address within a sector/block that is being programmed or
erased and not a protected sector/block. Otherwise, DATA# polling may give an inaccurate result if the
address used is in a protected block.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant
of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output,
it may read the status of valid data. Even if the device has completed the embedded operations and DQ7
has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be
read on the subsequent read attempts.
The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing
diagram is shown in Figure 8.
DQ6: Toggle Bit I
The EN39SL800 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device at
any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the
embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read on
the next successive attempts. During embedded Programming, the Toggle Bit is valid after the rising edge
of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after
the rising edge of the sixth WE# pulse for sector/block erase or chip erase.
In embedded Programming, if the block being written to is protected, DQ6 will toggles for about 2
stop toggling without the data in the block having changed. In Sector/Block Erase or Chip Erase, if all
selected blocks are protected, DQ6 will toggle for about 100
μs. The chip will then return to the read mode
without changing data in all protected blocks.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in
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