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EN29PL032A Datasheet(PDF) 43 Page - Eon Silicon Solution Inc. |
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EN29PL032A Datasheet(HTML) 43 Page - Eon Silicon Solution Inc. |
43 / 52 page This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 43 EN29PL032A Rev. B, Issue Date: 2010/12/27 20.6 Erase/Program Operations Table 20.5 Erase and Program Operations Parameter Speed Options (ns) JEDEC Std Description 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 35 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 30 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 10 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 25 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH 1 tWHW H1 Programming Operation (Note 2) Typ 8 µs tWHWH 1 tWHW H1 Accelerated Programming Operation (Note 2) Typ 7 µs tWHWH 2 tWHW H2 Sector Erase Operation (Note 2) Typ 0.1 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns Max 90 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 35 ns tPSL Program Suspend Latency Max 35 µs tESL Erase Suspend Latency Max 35 µs Notes: 1. Not 100% tested. 2. See Table 21.4 for more information. |
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