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EN29GL256H Datasheet(PDF) 25 Page - Eon Silicon Solution Inc.

Part No. EN29GL256H
Description  256 Megabit (32768K x 8-bit / 16384K x 16-bit) Flash Memory Page mode Flash Memory, CMOS 3.0 Volt-only
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw
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EN29GL256H Datasheet(HTML) 25 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
25
EN29GL256H/L
Rev. G, Issue Date: 2011/01/17
entire device. Table 3 indicate the address space that each sector occupies. The device address space
is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits required to
uniquely select a sector. ICC2 in “DC Characteristics” represents the active current specification for the
write mode. “AC Characteristics” contains timing specification tables and timing diagrams for write
operations.
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together
in parallel with a pull-up resistor to VCC. This feature allows the host system to detect when data is
ready to be read by simply monitoring the RY/BY# pin, which is a dedicated output and controlled by
CE# (not OE#).
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When
RESET# is driven low for at least a period of tRP (RESET# Pulse Width), the device immediately
terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores
all read/write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the
device is ready to accept another command sequence.
When RESET# is held at VSS, the device draws VCC reset current (ICC5). If RESET# is held at VIL, but
not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which
enables the system to read the boot-up firmware from the Flash memory upon a system reset.
Software Reset
Software reset is part of the command set that also returns the device to array read mode and must be
used for the following conditions:
1. To exit Autoselect mode
2. When DQ5 goes high during write status operation that indicates program or erase cycle was not
successfully completed
3. Exit sector lock/unlock operation.
4. To return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
5. After any aborted operations
The following are additional points to consider when using the reset command:
• This command resets the sectors to the read and address bits are ignored.
• Reset commands are ignored during program and erase operations.
• The reset command may be written between the cycles in a program command sequence before
programming begins (prior to the third cycle). This resets the sector to which the system was writing
to the read mode.
• If the program command sequence is written to a sector that is in the Erase Suspend mode, writing
the reset command returns that sector to the erase-suspend-read mode.
• The reset command may be written during an Autoselect command sequence.
• If a sector has entered the Autoselect mode while in the Erase Suspend mode, writing the reset
command returns that sector to the erase-suspend-read mode.
• If DQ1 goes high during a Write Buffer Programming operation, the system must write the “Write to
Buffer Abort Reset” command sequence to RESET the device to reading array data. The standard
RESET command does not work during this condition.


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