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EN25S16 Datasheet(PDF) 35 Page - Eon Silicon Solution Inc.

Part No. EN25S16
Description  16 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw
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EN25S16 Datasheet(HTML) 35 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
35
EN25S16
Rev. H, Issue Date: 2011/12/16
Write Suspend During Sector Erase or Block Erase
Issuing a Write Suspend instruction during Sector Erase or Block Erase allows the host to program or
read any sector that was not being erased. The device will ignore any programming commands
pointing to the suspended sector(s). Any attempt to read from the suspended sector(s) will out put
unknown data because the Sector or Block Erase will be incomplete.
To execute a Write Suspend operation, the host drives CS# low, sends the Write Suspend command
cycle (B0h), then drives CS# high. A cycle is two nibbles long, most significant nibble first. The
Suspend Status register indicates that the erase has been suspended by changing the WSE bit from
“0” to “1”, but the device will not accept another command until it is ready. To determine when the
device will accept a new command, poll the WIP bit in the Suspend Status register or wait after issue
program suspend command, latency time 20us is needed before issue another command. For
“Suspend to Read”, “Resume to Read”, “Resume to Suspend” timing specification please note Figure
22.1, 22.2 and 22.3.
Write Suspend During Page Programming
Issuing a Write Suspend instruction during Page Programming allows the host to erase or read any
sector that is not being programmed. Erase commands pointing to the suspended sector(s) will be
ignored. Any attempt to read from the suspended page will output unknown data because the program
will be incomplete.
To execute a Write Suspend operation, the host drives CS# low, sends the Write Suspend command
cycle (B0h), then drives CS# high. A cycle is two nibbles long, most significant nibble first. The
Suspend Status register indicates that the programming has been suspended by changing the WSP bit
from “0” to “1”, but the device will not accept another command until it is ready. To determine when the
device will accept a new command, poll the WIP bit in the Suspend Status register or wait after issue
program suspend command, latency time 20us is needed before issue another command. For
“Suspend to Read”, “Resume to Read”, “Resume to Suspend” timing specification please note Figure
22.1, 22.2 and 22.3.
The instruction sequence is shown in Figure 23.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 22.1 Suspend to Read Latency
Figure 22.2 Resume to Read Latency
Figure 22.3 Resume to Suspend Latency


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