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EN25S10 Datasheet(PDF) 12 Page - Eon Silicon Solution Inc.

Part No. EN25S10
Description  1 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector
Download  34 Pages
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw
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EN25S10 Datasheet(HTML) 12 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
12
EN25S10
Rev. F, Issue Date: 2011/11/07
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register
continuously, as shown in Figure 7.
Figure 7. Read Status Register Instruction Sequence Diagram
Table 6. Status Register Bit Locations
S7
S6
S5
S4
S3
S2
S1
S0
SRP
Status Register
Protect
OTP_LOCK
bit
(note 1)
BP2
(Block Protected
bits)
BP1
(Block Protected
bits)
BP0
(Block Protected
bits)
WEL
(Write Enable
Latch)
WIP
(Write In
Progress bit)
1 = status
register write
disable
1 = OTP
sector is
protected
(note 2 & 3)
(note 2 & 3)
(note 2 & 3)
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
Non-volatile bit
Reserved
bits
Reserved
bits
Non-volatile bit
Non-volatile bit
Non-volatile bit
volatile bit
volatile bit
Note :
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2.
After power-up, BP2, BP1 and BP0 are set to defaults 1 and protect full memory.
3. See the table 3 “
Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of
the area to be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0)
bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page


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