EDE2508ACSE-8E-E datasheet(31/81 Pages) ELPIDA

Part #	EDE2508ACSE-8E-E

Description	256M bits DDR2 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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EDE2508ACSE, EDE2516ACSE

Preliminary Data Sheet E0948E30 (Ver. 3.0)

31

Command Operation

Command Truth Table

The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.

CKE

Function

Symbol

Previou

s cycle

Current

cycle

/CS

/RAS /CAS /WE

BA0

BA1

A12 to

A11

A10

A0 to

A9

Notes

Mode register set

MRS

H

L

MRS OPCODE

1

Extended mode

register set (1)

EMRS

H

L

H

L

EMRS (1) OPCODE

1

Extended mode

register set (2)

EMRS

H

L

H

EMRS (2) OPCODE

1

Auto-refresh

REF

H

L

H

×

1

Self-refresh entry

SELF

H

L

H

×

1

Self-refresh exit

SELFX

L

H

×

1, 6

L

H

L

H

×

Single bank precharge

PRE

H

L

H

L

BA

×

L

×

1, 2

Precharge all banks

PALL

H

L

H

L

×

H

×

1

Bank activate

ACT

H

L

H

BA

RA

1, 2

Write

WRIT

H

L

H

L

BA

CA

L

CA

1, 2, 3

Write with auto precharge

WRITA

H

L

H

L

BA

CA

H

CA

1, 2, 3

Read

READ

H

L

H

L

H

BA

CA

L

CA

1, 2, 3

Read with auto precharge

READA H

H

L

H

L

H

BA

CA

H

CA

1, 2, 3

No operation

NOP

H

×

L

H

×

1

Device deselect

DESL

H

×

H

×

1

Power-down mode entry

PDEN

H

L

H

×

1, 4

H

L

H

×

Power-down mode exit

PDEX

L

H

×

1, 4

L

H

L

H

×

Remark: H = VIH. L = VIL.

× = VIH or VIL. BA = Bank Address, RA = Row Address, CA = Column Address

Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the

clock.

2. Bank select (BA0, BA1), determine which bank is to be operated upon.

3. Burst reads or writes should not be terminated other than specified as

″Reads interrupted by a Read″ in

burst read command [READ] or

″Writes interrupted by a Write″ in burst write command [WRIT].

4. The power-down mode does not perform any refresh operations. The duration of power-down is therefore

limited by the refresh requirements of the device. One clock delay is required for mode entry and exit.

5. The state of ODT does not affect the states described in this table. The ODT function is not available

during self-refresh.

6. Self-refresh exit is asynchronous.

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EDE2508ACSE-8E-E Datasheet(PDF) 31 Page - Elpida Memory

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