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LTC4278 Datasheet(PDF) 11 Page - Linear Technology |
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LTC4278 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 42 page  LTC4278 11 4278fc Information section for details. This pin is used for the UVLO function of the switching regulator. The PD interface section has an internal UVLO. SENSE–, SENSE+ (Pins 19, 20): Current Sense Inputs. These pins are used to measure primary-side switch cur- rent through an external sense resistor. Peak primary-side current is used in the converter control loop. Make Kelvin connections to the sense resistor RSENSE to reduce noise problems.SENSE–connectstotheGNDside.Atmaximum current (VCMP at its maximum voltage) SENSE pins have 100mV threshold. The signal is blanked (ignored) during the minimum turn-on time. CCMP (Pin 21): Load Compensation Capacitive Control. Connect a capacitor from CCMP to GND in order to reduce the effects of parasitic resistances in the feedback sensing path. A 0.1µF ceramic capacitor suffices for most applica- tions. Short this pin to GND when load compensation is not needed. RCMP (Pin 22): Load Compensation Resistive Control. Connect a resistor from RCMP to GND in order to com- pensate for parasitic resistances in the feedback sensing path. In less demanding applications, this resistor is not needed and this pin can be left open. See the Applications Information section for details. PIN FUNCTIONS PGDLY (Pin 23): Primary Gate Delay Control. Connect an external programming resistor (RPGDLY) to set delay from synchronous gate turn-off to primary gate turn-on. See the Applications Information section for details. PG (Pin 24): Primary Gate Drive. PG is the gate drive pin for the primary-side MOSFET switch. Large dynamic cur- rents flow during voltage transitions. See the Applications Information section for details. VNEG (Pins 26, 27): System Negative Rail. Connects VNEG to VPORTN through an internal power MOSFET. Pin 26 and Pin 27 must be electrically tied together at the package. PWRGD (Pin 29): Power Good Output, Open-Collector. High impedance signals power-up completion. PWRGD is referenced to VNEG and features a 14V clamp. PWRGD (Pin 30): Complementary Power Good Output, Open-Drain.Lowimpedancesignalspower-upcompletion. PWRGD is referenced to VPORTN. VPORTP (Pin 32): Positive Power Input. Tie to the input port power through the input diode bridge. Exposed Pad (Pin 33): Ground. This is the negative rail connection for both signal ground and gate driver grounds of the flyback controller. This pin should be connected to VNEG. |
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