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LTC4090 Datasheet(PDF) 27 Page - Linear Technology |
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LTC4090 Datasheet(HTML) 27 Page - Linear Technology |
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27 / 52 page  LTC4155 27 4155fc as explained in the Alternate Default Input Current Limit section of Operation. Thus, the contents of these registers may be different from the last value written by the bus master, and reading back the contents may be useful to determine the state of the system. When the contents of the sub address pointer register point to a read-only status register, the data returned is a snapshot of the state of the LTC4155 at a particular instant in time. If no interrupt requests are pending, the status data is sampled when the LTC4155 acknowledges its read address, just before the LTC4155 begins data transmis- sion during a bus read operation. When an unmasked interrupt event takes place, the IRQ pin is driven low and data is latched in the three read-only status registers at that moment. Any subsequent read operation from any status registers will return this frozen data to facilitate determination of the cause of the interrupt request. After the bus master clears the LTC4155 interrupt request, the status latches are cleared. Bus read operations will then again return either a snapshot of the data at the read ad- dress acknowledge, or at the time of the next interrupt assertion, whichever comes first. SMBus Protocol Compatibility The SMBus specification is generally compatible with the I2C bus specification, but extends beyond I2C to define and standardize specific protocol formats for various types of transactions. The LTC4155 I2C interface is fully compatible with four of the protocols defined by the SMBus speci- fication. All control and status features of the LTC4155 can be accessed using the SMBus protocols, although if high bus utilization is a concern, certain operations can be accomplished more efficiently by I2C bus operations that do not adhere to any of the SMBus defined protocols. SMBus Write Byte Protocol 171 1 8 1 8 1 1 S SLAVE ADDRESS WR A COMMAND CODE A DATA BYTE A P The SMBus write byte protocol can be used to modify the contents of any single control register in the LTC4155. The transaction is initiated by the bus master with a START condition. The SMBus slave address corresponds to the LTC4155 write address, which is 0x09 when interpreted as a 7-bit word (0b 000 1001), followed by WR (value 0b0). The LTC4155 will acknowledge its write address. The SMBus command code corresponds to the sub address pointer value and will be written to the sub address pointer register in the LTC4155. Only the register locations with write access (0x00 to 0x02, 0x06 to 0x07) are meaningful values for the sub address pointer when using this protocol. The LTC4155 will acknowledge the SMBus command code byte. The SMBus data byte corresponds to the command data to be written to the location pointed to by the sub address pointer register. The LTC4155 will acknowledge the SMBus data byte. The STOP condition at the end of the sequence will force an update to the command registers, causing the new command data to take immediate effect. SMBus Read Byte Protocol 17 1 1 8 1 1 7 1 1 8 1 1 S SLAVE ADDRESS WR A COMMAND CODE A Sr SLAVE ADDRESS RD A DATA BYTE AP The SMBus read byte protocol can be used to read the contents of any one of the seven control or status regis- ters with one bus transaction. The transaction is initiated by the bus master with a START condition. The SMBus slave address corresponds to the LTC4155 write address, which is 0x09 when interpreted as a 7-bit word (0b 000 1001), followed by WR (value 0b0). The LTC4155 will acknowledge its write address. The SMBus command code corresponds to the sub address pointer value and will be written to the sub address pointer register in the LTC4155. The LTC4155 will acknowledge the SMBus command code byte. The master then issues a repeat START condition, followed by the LTC4155 slave address (0x09) and RD (0b1). The LTC4155 will acknowledge its read address. At this time the bus master becomes a receiver while continuing to clock SCL. The LTC4155 becomes a slave transmitter and controls SDA to place data on the bus. Following the single data byte, the bus master has the option of transmitting either an ACK or a NACK bit. According to the I2C specification, a master must transmit a NACK at the end of a read transaction to instruct the slave to terminate data transmission. Because the LTC4155 terminates data transmission after one byte in all cases, whether the bus master transmits an ACK or OPERATION |
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Similar Description - LTC4090 |
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