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LTC2204 Datasheet(PDF) 17 Page - Linear Technology |
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LTC2204 Datasheet(HTML) 17 Page - Linear Technology |
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17 / 24 page  LTC2201 17 2201f Data Format The LTC2201 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resis- tor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the MODE pin. Table 1. MODE Pin Function MODE OUTPUT FORMAT CLOCK DUTY CYCLE STABILIZER 0(GND) Offset Binary Off 1/3VDD Offset Binary On 2/3VDD 2’s Complement On VDD 2’s Complement Off Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. A logic high on the OF pin indicates an overflow or underflow. Output Clock The ADC has a delayed version of the CLK input available as a digital output. Both a noninverted version, CLKOUT+ and an inverted version CLKOUT– are provided. The CLKOUT+/CLKOUT– can be used to synchronize the con- verter data to the digital system. This is necessary when using a sinusoidal clock. Data can be latched on the rising edge of CLKOUT+ or the falling edge of CLKOUT–. CLKOUT+ falls and CLKOUT– rises as the data outputs are updated. DIGITAL OUTPUTS Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer in CMOS Mode. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2201 should drive a small capaci- tive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as a ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43Ω on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. 2201 F09 OVDD VDD VDD 0.1μF TYPICAL DATA OUTPUT OGND 43Ω OVDD 0.5V TO 3.6V PREDRIVER LOGIC DATA FROM LATCH LTC2201 Figure 9. Equivalent Circuit for a Digital Output Buffer APPLICATIONS INFORMATION |
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