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LTC2369-18 Datasheet(PDF) 14 Page - Linear Technology |
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LTC2369-18 Datasheet(HTML) 14 Page - Linear Technology |
14 / 24 page LTC2369-18 14 236918fa APPLICATIONS INFORMATION Power Supply Sequencing The LTC2369-18 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2369-18 has a power-on-reset (POR) circuit that will reset the LTC2369-18 at initial power-up or whenever the power supply voltage drops below 1V. Once the supply voltage re-enters the nominal supply voltage range, the POR will reinitialize the ADC. No conversions should be initiated until 20μs after a POR event to ensure the reinitialization period has ended. Any conversions initiated before this time will produce invalid results. TIMING AND CONTROL CNV Timing The LTC2369-18 conversion is controlled by CNV. A ris- ing edge on CNV will start a conversion and power up the LTC2369-18. Once a conversion has been initiated, it cannot be restarted until the conversion is complete. For optimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress. To ensure that no errors occur in the digitized results, any additional transitions on CNV should occur within 40ns from the start of the conversion or after the conversion has been completed. Once the conversion has completed, the LTC2369-18 powers down and begins acquiring the input signal. Internal Conversion Clock The LTC2369-18 has an internal clock that is trimmed to achieve a maximum conversion time of 412ns. With a min- imum acquisition time of 200ns, throughput performance of 1.6Msps is guaranteed without any external adjustments. Auto Power-Down The LTC2369-18 automatically powers down after a conversion has been completed and powers up once a new conversion is initiated on the rising edge of CNV. During power down, data from the last conversion can be clocked out. To minimize power dissipation during Figure 9. Power Supply Current of the LTC2369-18 Versus Sampling Rate SAMPLING RATE (kHz) 0 4 6 1600 236918 F09 2 0 400 800 1200 200 600 1000 1400 8 3 5 1 7 IVDD IREF IOVDD power down, disable SDO and turn off SCK. The auto power-down feature will reduce the power dissipation of the LTC2369-18 as the sampling frequency is reduced. Since power is consumed only during a conversion, the LTC2369-18 remains powered down for a larger fraction of the conversion cycle (tCYC) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in Figure 9. DIGITAL INTERFACE The LTC2369-18 has a serial digital interface. The flexible OVDD supply allows the LTC2369-18 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The serial output data is clocked out on the SDO pin when an external clock is applied to the SCK pin if SDO is enabled. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 100MHz, a 1.6Msps throughput is still achieved. The serial output data changes state on the rising edge of SCK and can be captured on the falling edge or next rising edge of SCK. D17 remains valid till the first rising edge of SCK. The serial interface on the LTC2369-18 is simple and straightforward to use. The following sections describe the operation of the LTC2369-18. Several modes are provided depending on whether a single or multiple ADCs share the SPI bus or are daisy chained. |
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