6

5

4

1

2

3

IN+

IN-

GND

VDD

OUTH

OUTL

UCC27511

R1

R2

Q1

IN+

D1

C1

+

VOUT

VSOURCE

L1

C2

V+

4.5 V to 18 V

Non-Inverting Input

6

5

4

1

2

3

IN+

IN-

GND

VDD

OUTH

OUTL

UCC27511

R1

R2

Q1

IN-

D1

C1

+

VOUT

VSOURCE

L1

C2

V+

4.5 V to 18 V

Inverting Input

UCC27511

SLUSAW9B – FEBRUARY 2012 – REVISED MARCH 2012

www.ti.com

Typical Application Diagrams

DESCRIPTION (CONT.)

UCC27511 features a dual-input design which offers flexibility of implementing both inverting (IN- pin) and non-

inverting (IN+ pin) configuration with the same device. Either IN+ or IN- pin can be used to control the state of

the driver output. The unused input pin can be used for enable/disable function. For safety purpose, internal pull-

up and pull-down resistors on the input pins ensure that outputs are held low when input pins are in floating

condition. Hence the unused input pin cannot be left floating and needs to be properly biased to ensure that

driver output is in enabled for normal operation.

The input pin threshold of the UCC27511 device is based on TTL/CMOS-compatible low-voltage logic which is

fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers

excellent noise immunity.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

OPERATING

PEAK CURRENT

INPUT THRESHOLD

PART NUMBER

PACKAGE

TEMPERATURE RANGE,

(SOURCE/SINK)

LOGIC

CMOS/TTL-Compatible

4-A/8-A

UCC27511DBV

SOT-23 6-pin

(low voltage, independent

-40°C to 140°C

(Asymmetrical Drive)

of VDD bias voltage)

(1)

For the most current package and ordering information, see Package Option Addendum at the end of this document.

(2)

All packages use Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be

compatible with either lead free or Sn/Pb soldering operations. DRS package is rated MSL level 2.

Table 1. UCC2751x Product Family Summary

PART NUMBER

PACKAGE

PEAK CURRENT

INPUT THRESHOLD LOGIC

(SOURCE/SINK)

UCC27511DBV

SOT-23, 6 pin

4-A/8-A

CMOS/TTL-Compatible

(Asymmetrical Drive)

(low voltage, independent of VDD

3 mm x 3 mm WSON, 6 pin

bias voltage)

3 mm x 3 mm WSON, 6 pin

4-A/4-A

(Symmetrical Drive)

SOT-23, 5 pin

SOT-23, 5 pin

CMOS

(follows VDD bias voltage)

SOT-23, 5 pin

(1)

2

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