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TWL6041BYFFT Datasheet(PDF) 2 Page - Texas Instruments |
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TWL6041BYFFT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 9 page TWL6041 SWCS058B – AUGUST 2010 – REVISED DECEMBER 2011 www.ti.com DESCRIPTION The TWL6041 is an audio codec with a high level of integration providing analog audio codec functions for portable applications, as shown in Figure 1. It contains multiple audio analog inputs and outputs, as well as microphone biases and accessory detection. It is connected to the OMAP4 host processor through a proprietary PDM interface for audio data communication enabling partitioning with optimized power consumption and performance. Multichannel audio data is multiplexed to a single wire for downlink (PDML) and uplink (PDMUL). The OMAP4 device provides a TWL6041 with five PDM audio-input channels (DL0 –DL4). Channels DL0–DL3 are connected to four parallel DAC channels multiplexed to stereo headphone (HSL, HSR), stereo speaker (HFL, HFR), and earpiece (EAR) or stereo line outputs (AUXL, AUXR). The stereo headphone path has a low-power (LP) mode operating from a 32-kHz sleep clock to enable over 100 hours of MP3 playback time. Very-high dynamic range of 104 dBA is achieved when using the system clock input and DAC path high-performance (HP) mode. Class-AB headphone drivers provide a 1-Vrms output and are ground centered for capless connection to headphone, thus enabling system size and cost reduction. The earpiece driver is a differential class-AB driver with 2-Vrms capability to a typical 32- Ω load or 1.4-Vrms to a typical 16- Ω load. Stereo speaker path has filterless class-D outputs with 1.5-W capability per channel. Additionally, the 4- Ω load is supported. For output power maximization supply connection to an external boost is supported. Speaker drivers support also hearing aid coil loads. For vibrator and haptic feedback support TWL6041 has two PWM channels with independent input signals from DL4 or I2C. Vibra drivers are differential H-bridge outputs, enabling fast acceleration and deceleration of vibra motor. An external driver for a hearing aid coil or a piezo speaker requiring high voltage can be connected to line outputs. The TWL6041 supports three differential microphone inputs (MMIC, HMIC, SMIC) and a stereo line-input (AFML, AFMR) multiplexed to two parallel analog-to-digital converters (ADCs). The PDM output from the ADCs is transmitted to the OMAP4 through UL0 and UL1. AFML, AFMR inputs can also be looped to analog outputs (LB0, LB1). Two LDOs provide a voltage of 2.1 V to bias analog microphones (MBIAS and HBIAS). The maximum output current is 2 mA for each analog bias, allowing up to 2 microphones on one bias. Two LDOs provide a voltage of 1.8 V/1.85 V to bias digital microphones (DBIAS1 and DBIAS2). One bias generator can bias up several digital microphones at the same time, with a total maximum output current of 10 mA. The TWL6041 has an integrated negative charge pump and two LDOs (HS LDO and LS LDO) for high PSRR. The only external supply needed is 2.1 V, which is available from the 2.1-V DC-DC of TWL6030/6032 PMIC of OMAP. By powering audio from low-noise 2.1-V DC-DC of low power consumption, high dynamic range and high output swing at headset output are achieved. All other supply inputs can be directly connected to battery or system 1.8-V I/O. Two integrated phase-locked loops (PLLs) enable operatation from a 12/19.2/26/38.4-MHz system clock (MCLK) or, in LP playback mode, from a 32-kHz sleep clock (CLK32K). The frequency plan is based on a 48-kS/s audio data rate for all channels, and host processor uses sample-rate converters to interface with different sample rates (that is, 44.1 kHz). In the specific case of low-power audio playback, the 44.1-kS/s and 48-kS/s rates are supported by the TWL6041. Transitions between sample rates or input clocks are seamless. Accessory plug and unplug detections are supported (PLUGDET). Some headsets have a manual switch for submitting send/end signal to the terminal through the microphone input pin. This feature is supported by a periodic accessory button press detection to minimize current consumption in sleep mode. Detection cycle properties can be programmed according to system requirements. Figure 1 shows a simplified block diagram of the device. 2 Copyright © 2010–2011, Texas Instruments Incorporated |
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