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TPS51601ADRBR Datasheet(PDF) 10 Page - Texas Instruments |
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TPS51601ADRBR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 19 page PWM DRVL DRVH tDLY(rise) tNONOVLP 1.0 V tDLY(fall) tNONOVLP 1.0 V UDG-11129 DRVL turned OFF by zero-crossing tDLY(rise) tDLY(fall) PWM DRVH tNONOVLP 1.0 V UDG-11131 TPS51601A SLUSAP3 – MAY 2012 www.ti.com DETAILED DESCRIPTION UVLO The TPS51601A includes an undervoltage lockout circuit that disables the driver and external power FETs in an OFF state when the input supply voltage, (VVDD) is insufficient to drive external power FET reliably. During the power-up sequence, both gate drive outputs remain low until the VDD voltage reaches UVLO-H threshold, typically 3.7 V. Once the UVLO threshold is reached, the condition of the gate drive outputs is defined by the input PWM and SKIP signals. During the power-down sequence, the UVLO threshold is set lower, typically 3.5 V. PWM Input Once the input supply voltage is above the UVLO threshold, the gate drive outputs are defined by the PWM input and SKIP input. Prior to PWM going HIGH, both the gate drive outputs, (DRVH and DRVL) are held LOW. The DRVL is LOW until the first PWM HIGH pulse to support pre-biased start-up. Once PWM goes HIGH for the first time, DRVH goes HIGH. Then, when PWM goes LOW, DRVH goes LOW first. After the non-overlap time, DRVL goes HIGH. Figure 17. Continuous Conduction Mode Figure 18. Discontinuous Conduction Mode Waveforms Waveforms SKIP/FCCM Mode Operation The TPS51601A can be configured in two ways. When used as the external driver for Phase 1, this pin connects to the corresponding SKIP pin of the PWM controller. The SKIP pin is active low signal. This means when SKIP is low, then the zero crossing detection circuit of the driver is active. When SKIP is high, the zero-crossing detector is disabled and the converter operates in forced continuous conduction mode (FCCM). Adaptive Zero-Crossing The TPS51601A has an adaptive zero-crossing detector. Zero crossing accuracy is detected by checking the switch-node voltage at an appropriate time after the low-side FET is turned OFF by DRVL going low. Then the zero-crossing comparator offset is updated based on previous result. After several zero-crossing events, the comparator offset is optimized to give the best efficiency. Adaptive Dead-Time Control (Anti-Cross Conduction) The TPS51601A has an adaptive dead-time control logic to minimize the non-overlap time between DRVH and DRVL signals. The internal signal to the low-side driver goes HIGH only when the DRVH-SW voltage goes below approximately 1 V and DRVH goes below approximately 1 V to ensure the high-side MOSFET has turned OFF. Additional driver delays ensure that there is some non-overlap time between DRVH falling edge and DRVL rising edge. Similarly, the internal signal to the DRVH goes high only after DRVL-GND goes below 1 V. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A |
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