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INA3221AIRGVT Datasheet(PDF) 27 Page - Texas Instruments

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Part # INA3221AIRGVT
Description  Triple-Channel, High-Side Measurement, Shunt and Bus Voltage Monitor
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

INA3221AIRGVT Datasheet(HTML) 27 Page - Texas Instruments

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INA3221
www.ti.com
SBOS576 – MAY 2012
Mask/Enable Register (Address = 0Fh, Read/Write)
BIT
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
SCC1
SCC2
SCC3
WEN
CEN
CF1
CF2
CF3
SF
WF1
WF2
WF3
PVF
TCF
CVRF
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
VALUE
Bits[14:12]
SCC: Summation Channel Control
These bits determine which shunt voltage measurement channels are enabled to fill the Shunt Voltage Sum
register. The selection of these bits does not impact the individual channel enable or disable status or the
corresponding channel measurements. The corresponding bit is used to select if the channel is used to fill the
Shunt Voltage Sum Register.
0 = Disabled (default)
1 = Enabled
Bit 11
WEN: Warning Alert Latch Enable configures the latching feature of the Warning Alert pin.
0 = Transparent (default)
1 = Latch enabled
Bit 10
CEN: Critical Alert Latch Enable configures the latching feature of the Critical Alert pin.
0 = Transparent (default)
1 = Latch enabled
Bits[9:7]
CF: Critical Alert Flag Indicator
These bits are asserted if the corresponding channel measurement has exceeded the Critical Alert limit resulting in
the Critical Alert pin being asserted. These bits can be read back to determine which channel caused the Critical
Alert. The Critical Alert Flag bits are cleared when the Mask/Enable Register is read back.
Bit 6
SF: Summation Alert Flag Indicator
This bit is asserted if the Shunt Voltage Sum register exceeds the Shunt Voltage Sum Limit register. If the
Summation Alert Flag is asserted, the Critical Alert pin is also asserted. The Summation Alert Flag bit is cleared
when the Mask/Enable Register is read back.
Bits[5:3]
WF: Warning Alert Flag Indicator
These bits are asserted if the corresponding channel’s averaged measurement has exceeded the Warning Alert
limit resulting in the Warning Alert pin being asserted. These bits can be read back to determine which channel
caused the Warning Alert. The Warning Alert Flag bits clear when the Mask/Enable Register is read back.
Bit 2
PVF: Power Valid Alert Flag Indicator
This bit can be used to be able to determine if the Power Valid Alert pin has been asserted through software rather
than hardware. The bit setting corresponds to the status of the Power Valid Alert pin. This bit does not clear until
the condition that caused the alert is removed and the Power Valid Alert pin has cleared.
Bit 1
TCF: Timing Control Alert Flag Indicator
This bit can be used to be able to determine if the Timing Control Alert pin has been asserted through software
rather than hardware. The bit setting corresponds to the status of the Timing Control Alert pin. This bit does not
clear once it has been asserted unless the power is recycled or a software reset is issued. The default state for the
Timing Control Alert Flag is High.
Bit 0
CVRF: Conversion Ready Flag
Although the INA3221 can be read at any time, and the data from the last conversion is available, the Conversion
Ready bit is provided to help coordinate single-shot conversions. The Conversion bit is set after all conversions are
complete. Conversion Ready clears under the following conditions:
Writing the Configuration Register (except for power-down or disable mode selections).
Reading the Mask/Enable Register.
This register selects which function is enabled to control the Critical Alert and Warning Alert pins and how each
Warning Alert responds to the corresponding channel. Reading the Mask/Enable Register clears any flag results
present. Writing to this register does not clear the flag bit status. To ensure that there is no uncertainty in the
warning function setting that resulted in a flag bit being set, the Mask/Enable Register should be read from to
clear the flag bit status before changing the warning function setting.
Power Valid Upper Limit Register (Address = 10h, Read/Write)(1)
BIT
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
PVU12
PVU11
PVU10
PVU9
PVU8
PVU7
PVU6
PVU5
PVU4
PVU3
PVU2
PVU1
PVU0
(1)
Power-on reset value is 2710h (10.000 V)
Copyright © 2012, Texas Instruments Incorporated
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