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DRV110 Datasheet(PDF) 7 Page - Texas Instruments |
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DRV110 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 17 page I PEAK I HOLD t KEEP t I SOLENOID EN t 5 KEEP KEEP s t s C F 10 F é ù = × é ù é ù ë û ë û ê ú ë û PEAK PEAK SENSE PEAK 1 900mA I 66.67k ;66.67k R 2M R R W = × × W W < < W DRV110 www.ti.com SLVSBA8 – MARCH 2012 FUNCTIONAL DESCRIPTION DRV110 controls the current through the solenoid as shown in Figure 3. Activation starts when EN pin voltage is pulled high either by an external driver or internal pull-up. In the beginning of activation, DRV110 allows the load current to ramp up to the peak value IPEAK and it regulates it at the peak value for the time, tKEEP, before reducing it to IHOLD. The load current is regulated at the hold value as long as the EN pin is kept high. The initial current ramp-up time depends on the inductance and resistance of the solenoid. Once EN pin is driven to GND, DRV110 allows the solenoid current to decay to zero. Figure 3. Typical Current Waveform Through the Solenoid tKEEP is set externally by connecting a capacitor to the KEEP pin. A constant current is sourced from the KEEP pin that is driven into an external capacitor resulting in a linear voltage ramp. When the KEEP pin voltage reaches 100 mV, the current regulation reference voltage, VREF, is switched from VPEAK to VHOLD. Dependency of tKEEP from the external capacitor size can be calculated by: (1) The current control loop regulates, cycle-by-cycle, the solenoid current by sensing voltage at the SENSE pin and controlling the external switching device gate through the OUT pin. During the ON-cycle, the OUT pin voltage is driven and kept high (equal to VIN voltage) as long as the voltage at the SENSE pin is less than VREF allowing current to flow through the external switch. As soon as the voltage at the SENSE pin is above VREF, the OUT pin voltage is immediately driven and kept low until the next ON-cycle is triggered by the internal PWM clock signal. In the beginning of each ON-cycle, the OUT pin voltage is driven and kept high for at least the time determined by the minimum PWM signal duty cycle, DMIN. VPEAK and VHOLD depend on fixed resistance values RPEAK and RHOLD as shown in Figure 4. If the PEAK pin is connected to ground, the peak current reference voltage, VPEAK, is at it’s default value (internal setting). The VPEAK value can alternatively be set by connecting an external resistor to ground from the PEAK pin. For example, if a 50-k Ω (= RPEAK) resistor is connected between PEAK and GND, and RSENSE = 1 Ω, then the externally set IPEAK level will be 900 mA. If RPEAK = 200 kΩ and RSENSE = 1 Ω, then the externally set IPEAK level will be 300 mA. In case RSENSE = 2 Ω instead of 1 Ω, then IPEAK = 450 mA (when RPEAK = 50 kΩ) and IPEAK = 150 mA (when RPEAK = 200 kΩ). External setting of the HOLD current, IHOLD, works in the same way, but the current levels are 1/6 of the IPEAK levels. External settings for IPEAK and IHOLD are independent of each other. If RPEAK is decreased below 33.33 kΩ (typ value), then the reference is clamped to the internal setting. The same is valid for RHOLD and IHOLD. IPEAK and IHOLD values can be calculated by using the formula below. (2) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): DRV110 |
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