CDCM6208V2RGZR datasheet(65/78 Pages) TI

Part #	CDCM6208V2RGZR

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

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SCAS931A – MAY 2012 – REVISED JUNE 2012

Table 37. Register 18 (continued)

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

13

RESERVED

This bit must be set to 0

Output channel 7 fractional divider's 3-b pre-divider setting(this pre-

divider is bypassed if Q18.9 = 0)

000

→ Divide by 2

12:10

PRE_DIV_CH7[2:0]

001

→ Divide by 3

111

→ Divide by 1; (only for CDCM6208V1 with f VCO ≤ 2.4 GHz)

All other combinations reserved

Output channel 7 fractional divider enable: 0

→ Disable, 1 →

9

EN_FRACDIV_CH7

Enable

8

LVCMOS_SLEW_CH7

Output channel 7 LVCMOS output slew: 0

→ Normal, 1 → Slow

Output channel 7 negative-side LVCMOS enable: 0

→ Disable, 1 →

7

EN_LVCMOS_N_CH7

Enable (Negative side can only be enabled if positive side is

Output Channel 7

enabled)

Output channel 7 positive-side LVCMOS enable: 0

→ Disable, 1 →

6

EN_LVCMOS_P_CH7

Enable

5

RESERVED

This bit must be set to 0

Output channel 7 type selection:00 or 01

→ LVDS, 10 → LVCMOS,

4:3

SEL_DRVR_CH7[2:0]

11

→ HCSL

Output channel 7 enable: 00

→ Disable, 01 → Enable, 10 → Drive

2:1

EN_CH7[1:0]

static low, 11

→ Drive static high

Output channel 7 Supply Voltage Selection: 0

→ 1.8 V, 1 → 2.5/3.3

0

SUPPLY_CH7 (1)

V

(1)

It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.

Table 38. Register 19

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15

RESERVED

This bit must be set to 0

14

RESERVED

This bit must be set to 0

13

RESERVED

This bit must be set to 0

12

RESERVED

This bit must be set to 0

Output channel 7 8-b integer divider setting

11:4

OUTDIV7[7:0]

(Divider value is register value +1)

Output Channel 7

3:0

FRACDIV7[19:16]

Output channel 7 20-b fractional divider setting, bits 19-16

Table 39. Register 20

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15:0

FRACDIV7[15:0]

Output Channel 7

Output channel 7 20-b fractional divider setting, bits 15-0

Table 40. Register 21 (Read Only)

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15

RESERVED

This bit will read a 0

14

RESERVED

This bit will read a 0

13

RESERVED

This bit will read a 0

12

RESERVED

This bit will read a 0

11

RESERVED

This bit will read a 0

10

RESERVED

This bit will read a 0

9

RESERVED

This bit will read a 0

8

RESERVED

This bit will read a 0

7

RESERVED

This bit will read a 0

6

RESERVED

This bit will read a 0

5

RESERVED

This bit will read a 0

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