CDCM6208V2RGZR datasheet(50/78 Pages) TI

Part #	CDCM6208V2RGZR

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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5

4

3

2

Reg05

Register Number (s)

Bit Number(s)

R05 .2

Device

Control

And

Status

STATUS0

STATUS1/PIN0

PDN

RESETN/PWR

SCL/PIN4

SDI/SDA/PIN1

SDO/AD0/PIN2

SCS/AD1/PIN3

SI_MODE0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg1

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg2

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg3

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 20

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 21

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 22

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 23

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg30

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg31

REGISTER SPACE

Device

Hardware

SPI/

I2C

Port

Control/

Status

Pins

SPI: SI_MODE[1:0]=00;

I2C: SI_MODE[1:0]=01;

Pin Mode: SI_MODE[1:0]=10

SI_MODE1

Comm

Select

CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

Figure 42. CDCM6208 Interface and Control Block

Within this register space, there are certain bits that have read/write access. Other bits are read-only (an attempt

to write to a read only bit will not change the state of the bit).

REGISTER FILE REFERENCE CONVENTION

Figure 43 shows the method that this document employs to refer to an individual register bit or a grouping of

register bits. If a drawing or text references an individual bit the format is to specify the register number first and

the bit number second. The CDCM6208 contains 21 registers that are 16 bits wide. The register addresses and

the bit positions both begin with the number zero (0). A period separates the register address and bit address.

The first bit in the register file is address 'R0.0' meaning that it is located in Register 0 and is bit position 0. The

last bit in the register file is address R31.15 referring to the 16thbit of register address 31 (the 32ndregister in the

device

Figure 43. CDCM6208 Register Reference Format

SPI - SERIAL PERIPHERAL INTERFACE

To enable the SPI port, tie the communication select pins SI_MODE[1:0] to ground. SPI is a master/slave

protocol in which the host system is always the master; therefore, the host always initiates communication

to/from the device. The SPI interface consists of four signal pins. The device SPI address is 0000.

Table 14. SERIAL PORT SIGNALS IN SPI MODE

I/O

DESCRIPTION

NAME

NUMBER

SDI/SDA/PIN1

2

Input

SDI: SPI Serial Data Input

SDO/AD0/PIN2

3

Output

SDO: SPI Serial Data

SCS/AD1/PIN3

4

Input

SCS: SPI Latch Enable

SCL/PIN4

5

Input

SCL: SPI/I2C Clock

50

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