CDCM6208 datasheet(48/78 Pages) TI

Part #	CDCM6208

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

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Table 12. CDCM6208V2 Loop Filter Recommendation for Pin Mode

Status Pins Definition

The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by

reading device registers or by at the status pins STATUS1, and STATUS0. Register 3[12:7] allows to customize

which of the vitals are mapped out to these two pins. Table 13 lists the three events that can be mapped to each

status pin and which can also be read in the register space.

Table 13. CDCM6208 Status Pin Definition List

STATUS

SIGNAL Type

SIGNAL NAME

REGISTER BIT Description

SIGNAL Name

NO.

SEL_REF

LVCMOS

STATUS0/1

Reg 3.12

Indicates Reference Selected for PLL:

Reg 3.9

0

→ Primary input selected to drive PLL

1

→ Secondary input selected to drive PLL

LOS_REF

LVCMOS

STATUS0/1

Reg 3.11

Loss of selected reference input observed at active input:

Reg 3.8

0

→ Reference input present

1

→ Loss of reference input

Important Note 1: For LOS_REF to operate properly, the secondary

input SEC_IN must be enabled. Set register Q4.5=1. If register

Q4.5 is set to zero, LOS_REF will output a static high signal

regardless of the actual input signal status on PRI_IN.

48

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