MCM67D709

2

MOTOROLA FAST SRAM

BLOCK DIAGRAM

K

9

9

9

WRITE

DRIVER

A0 – A16

W

PIE

SIE

POE

SOE

128K x 9 ARRAY

DATA

REGISTER

DATA

REGISTER

DATA

LATCH

DATA

LATCH

SENSE

AMPLIFIER

SDQ0 – SDQ7, SDQP

PDQ0 – PDQ7, PDQP

W

PIE

SIE

POE

SOE

Mode

Memory Subsystem

Cycle

PDQ0 – PDQ7,

PDQP Output

SDQ0 – SDQ7,

SDQP Output

Notes

1

1

1

0

1

Read

Processor Read

Data Out

High–Z

3

1

1

1

1

0

Read

Copy Back

High–Z

Data Out

3

1

1

1

0

0

Read

Dual Bus Read

Data Out

Data Out

3

1

X

X

1

1

Read

NOP

High–Z

High–Z

X

0

0

X

X

N/A

NOP

High–Z

High–Z

2, 4

0

0

1

1

1

Write

Processor Write Hit

Data In

High–Z

2, 5

0

1

0

1

1

Write

Allocate

High–Z

Data In

2, 5

0

0

1

1

0

Write

Write Through

Data In

Stream Data

2, 6

0

1

0

0

1

Write

Allocate With Stream

Stream Data

Data In

2, 6

1

0

1

1

0

N/A

Cache Inhibit Write

Data In

Stream Data

2, 6

1

1

0

0

1

N/A

Cache Inhibit Read

Stream Data

Data In

2, 6

0

1

1

X

X

N/A

NOP

High–Z

High–Z

4

X

0

1

0

0

N/A

Invalid

Data In

Stream

2, 7

X

0

1

0

1

N/A

Invalid

Data In

High–Z

2, 7

X

1

0

0

0

N/A

Invalid

Stream

Data In

2, 7

X

1

0

1

0

N/A

Invalid

High–Z

Data In

2, 7

NOTES:

1. A ‘0’ represents an input voltage

≤ VIL and a ‘1’ represents an input voltage ≥ VIH. All inputs must satisfy the specified setup and hold times

for the falling or rising edge of K. Some entries in this truth table represent latched values. Other possible combinations of control inputs not

covered by this note or the table above are not supported and the RAMs behavior is not specified.

2. If either IE signal is sampled low on the rising edge of clock, the corresponding OE is a don’t care, and the corresponding outputs are

High–Z.

3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM.

4. No RAM cycle is performed.

5. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports (PDQ0 – PDQ7 and

PDQP or SDQ0 – SDQ7 and SPDQ), and written into the RAM.

6. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other

I/O port.

7. Data contention will occur.