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MAX98355A Datasheet(PDF) 26 Page - Maxim Integrated Products |
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MAX98355A Datasheet(HTML) 26 Page - Maxim Integrated Products |
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26 / 34 page  ���������������������������������������������������������������� Maxim Integrated Products 26 MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Standby Mode If BCLK stops toggling, the ICs automatically enter standby mode. In standby mode, the Class D speaker is turned off and the outputs go into a high-impedance state, ensuring that unwanted current is not transferred to the load during this condition. Standby mode should not be used in place of the shutdown mode, as the shutdown mode provides the lowest power consumption and the best power-on/off click-and-pop performance. DAC Digital Filters The DAC features a digital lowpass filter that is automati- cally configured for voice playback or music playback based on the sample rate that is used. This filter elimi- nates the effect of aliasing and any other high-frequency noise that might otherwise be present. Table 4 shows the digital filter settings that are automatically selected. SD_MODE and Shutdown Operation The ICs feature a low-power shutdown mode, drawing less than 0.6FA (typ) of supply current. During shutdown, all internal blocks are turned off, including setting the output stage to a high-impedance state. Drive SD_MODE low to put the ICs into shutdown. The state of SD_MODE determines the audio channel that is sent to the amplifier output (Table 5). Drive SD_MODE high to select the left word of the stereo input data. Drive SD_MODE high through a sufficiently small resistor to select the right word of the stereo input data. Drive SD_MODE high through a sufficiently large resistor to select both the left and right words of the stereo input data ((left + right)/2). RLARGE and RSMALL are determined by the VDDIO voltage (logic voltage from control interface) that is driving SD_MODE according to the following two equations: RSMALL (kI) = 98.5 x VDDIO - 100 RLARGE (kI) = 222.2 x VDDIO - 100 Table 4. Digital Filter Settings Table 5. SD_MODE Control Table 6. Examples of SD_MODE Pullup Resistor Values LRCLK FREQUENCY -3dB CUTOFF FREQUENCY RIPPLE LIMIT CUTOFF FREQUENCY STOPBAND CUTOFF FREQUENCY STOPBAND ATTENUATION (dB) fLRCLK < 30kHz 0.446 x fLRCLK 0.443 x fLRCLK 0.464 x fLRCLK 75 30kHz < fLRCLK < 50kHz 0.47 x fLRCLK 0.43 x fLRCLK 0.58 x fLRCLK 60 fLRCLK > 50kHz 0.31 x fLRCLK 0.24 x fLRCLK 0.477 x fLRCLK 60 SD_MODE STATUS SELECTED CHANNEL High VSD_MODE > B2 trip point (1.4V typ) Left Pullup through RSMALL B2 trip point (1.4V typ) > VSD_MODE > B1 trip point (0.77V typ) Right Pullup through RLARGE B1 trip point (0.77 typ) > VSD_MODE > B0 trip point (0.16V typ) (Left + right)/2 Low B0 trip point (0.16V typ) > VSD_MODE Shutdown LOGIC VOLTAGE LEVEL (VDDIO) (V) RSMALL (kI, 1% TOLERANCE) RLARGE (kI, 1% TOLERANCE) 1.8 76.8 300 3.3 226 634 |
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