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DM9161CIEP Datasheet(PDF) 41 Page - Davicom Semiconductor, Inc. |
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DM9161CIEP Datasheet(HTML) 41 Page - Davicom Semiconductor, Inc. |
41 / 47 page DM9161CI 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 43 Final Version: DM9161CI-DS-F01 February 22, 2012 9.4.10 MII 100BASE-TX Receive Timing Diagram RXCLK t2 t1 tTX pd RXD [0:3], RXDV, RXER CRS RX+/- tRX S tRX h t4 t3 COL t5 t5 tRXc tRXh 9.4.11 MII 10BASE-T Nibble Transmit Timing Parameters Symbol Parameter Min. Typ. Max. Unit Conditions tTXs TXD[0:3), TXEN, TXER Setup To TXCLK High 5 - - ns tTXh TXD[0:3], TXEN, TXER Hold From TXCLK High 5 - - ns t1 TXEN Sampled To CRS Asserted - 2 4 BT t2 TXEN Sampled To CRS De-asserted - 15 20 BT tTXpd TXEN Sampled To 10TXO Out (Tx Latency) - 2 4 BT 9 .4.12 MII 10BASE-T Nibble Transmit Timing Diagram TXCLK tTX h t2 tTX S t1 tTX pd TXD [0:3], TXEN, TXER CRS 10TX+/- |
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