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Electronic Components Datasheet Search |
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DM9006 Datasheet(PDF) 22 Page - Davicom Semiconductor, Inc. |
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DM9006 Datasheet(HTML) 22 Page - Davicom Semiconductor, Inc. |
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22 / 76 page 
DM9006 2-port Switch with Processor Interface 22 Preliminary datasheet DM9006-13-DS-P01 September 1, 2009 6.22 Receive Check Sum Control Status Register (32H) Bit Name Default Description 7 UDPS HP0,RO UDP Checksum Status 1: UDP packet checksum is fail. 0: UDP packet checksum is OK or it is not a UDP packet. 6 TCPS HP0,RO TCP Checksum Status 1: TCP packet checksum is fail. 0: TCP packet checksum is OK or it is not a TCP packet. 5 IPS HP0,RO IP Checksum Status 1: IP packet checksum is ail 0: IP packet checksum is OK or it is not an IP packet. 4 UDPP HP0,RO This is an UDP Packet 3 TCPP HP0,RO This is a TCP Packet 2 IPP HP0,RO This is an IP Packet 1 RCSEN HPS0,RW Receive Checksum Checking Enable When set, the checksum status will store in packet first byte of status header. 0 DCSE HPS0,RW Discard Checksum Error Packet When set, IP/TCP/UDP checksum field is error, this packet will be discarded. 6.23 uP Data Bus driving capability Register (38H) Bit Name Default Description 7 RESERVED 0,RW reserved 6:5 ISA_CURR P01,RW SD Bus Current Driving/Sinking Capability 00: 2mA 01: 4mA (default) 10: 6mA 11: 8mA 4:3 Reserved P0,RW Reserved 2 STEP P0,RW Data Bus Output stepping 1: disabled 0: enabled 1 IOW_SPIKE P0,RW Eliminate IOW spike 1: eliminate about 2ns IOW spike 0 IOR_SPIKE P1,RW Eliminate IOR spike 1: eliminate about 2ns IOR spike 6.24 IRQ Pin Control Register (39H) Bit Name Default Description 7:5 IRQ_DELAY PS0,RW IRQ Delayed Output Interval This field determines the IRQ delayed output interval in multiples of 40 milliseconds(ms) 1 IRQ_TYPE PET0,RW IRQ Pin Output Type Control 1: IRQ open-collector output 0: IRQ direct output |
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