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DM9006 Datasheet(PDF) 21 Page - Davicom Semiconductor, Inc.

Part No. DM9006
Description  10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface
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Maker  DAVICOM [Davicom Semiconductor, Inc.]
Homepage  http://www.davicom.com.tw
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DM9006 Datasheet(HTML) 21 Page - Davicom Semiconductor, Inc.

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DM9006
2-port Switch with Processor Interface
Preliminary datasheet
21
DM9006-13-DS-P01
September 1, 2009
7:0
MAB2
X,RW
Multicast Address Byte 2 (18H)
7:0
MAB1
X,RW
Multicast Address Byte 1 (17H)
7:0
MAB0
X,RW
Multicast Address Byte 0 (16H)
6.14 RX Packet Length Low Register ( 20H )
Bit
Name
Default
Description
7:0
RXPLL
PH,RO
RX Packet Length Low byte
6.15 RX Packet Length High Register ( 21H )
Bit
Name
Default
Description
7:0
RXPLH
PH,RO
RX Packet Length High byte
6.16 RX Additional Status Register ( 26H )
Bit
Name
Default
Description
7:4
RESERVED
0,RO
Reserved
1:0
RPTRS
PH,RO
uP received pointer status, only available when RX pointer restriction is enabled
(Reg27h.7=0).
00: Within buffer
01: End of buffer
1x: Exceed buffer
6.17 RX Additional Control Register ( 27H )
Bit
Name
Default
Description
7
RPRD
PHS0,RW
RX pointer restriction disable
6:0
RESERVED
0,RO
Reserved
6.18 Vendor ID Registers (28H~29H)
Bit
Name
Default
Description
7:0
VIDH
PE,0AH,RO
Vendor ID High Byte (29H)
7:0
VIDL
PE,46H.RO
Vendor ID Low Byte (28H)
6.19 Product ID Registers (2AH~2BH)
Bit
Name
Default
Description
7:0
PIDH
PE,90H,RO
Product ID High Byte (2BH)
7:0
PIDL
PE,06H.RO
Product ID Low Byte (2AH)
6.20 Chip Revision Register (2CH)
Bit
Name
Default
Description
7:0
CHIPR
02H,RO
CHIP Revision
6.21 Transmit Check Sum Control Register (31H)
Bit
Name
Default
Description
7~3
RESERVED
0,RO
Reserved
2
UDPCSE
HP0,RW
UDP Checksum Generation Enable
1
TCPCSE
HP0,RW
TCP Checksum Generation Enable
0
IPCSE
HP0,RW
IP Checksum Generation Enable


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