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DM9006 Datasheet(PDF) 19 Page - Davicom Semiconductor, Inc.

Part No. DM9006
Description  10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface
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Maker  DAVICOM [Davicom Semiconductor, Inc.]
Homepage  http://www.davicom.com.tw
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DM9006 Datasheet(HTML) 19 Page - Davicom Semiconductor, Inc.

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DM9006
2-port Switch with Processor Interface
Preliminary datasheet
19
DM9006-13-DS-P01
September 1, 2009
1
PRMSC
PHS0,RW
Promiscuous Mode
All received packets are accepted and save to receive memory without DA field filter.
0
RXEN
PHS0,RW
RX Enable
6.5 RX Status Register (06H)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
6
MF
0,RO
Multicast Frame
5:4
PKT_TYPE
0,RO
Received Frame Type
00: Reserved
01: IGMP packet
10: MLD packet
11: BPDU packet
3:2
SRCP
0,RO
Source Port Number
1
CE
0,RO
CRC Error
0
FOE
0,RO
FIFO Overflow Error
6.6 Receive Overflow Counter Register (07H)
Bit
Name
Default
Description
7
RXFU
PHS0,R/C
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
6:0
ROC
PHS0,R/C
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
6.7 Flow Control Register (0AH)
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
5
FLOW_EN
PHS0,RW
RX Flow Control Enable
Enables the pause packet for high/low water threshold control
4:0
RESERVED
0,RO
Reserved
6.8 EEPROM & PHY Control Register (0BH)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
6
EETYPE
0,RO
EEPROM Type
0: 93C46
1: 93C56
5
REEP
PH0,RW
Reload EEPROM. Driver needs to clear it up after the operation completes
4
WEP
PH0,RW
Write EEPROM Enable
3
EPOS
PH0,RW
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2
ERPRR
PH0,RW
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
1
ERPRW
PH0,RW
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.


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