Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

DM9006 Datasheet(PDF) 18 Page - Davicom Semiconductor, Inc.

Part No. DM9006
Description  10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface
Download  76 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  DAVICOM [Davicom Semiconductor, Inc.]
Homepage  http://www.davicom.com.tw
Logo 

DM9006 Datasheet(HTML) 18 Page - Davicom Semiconductor, Inc.

Zoom Inzoom in Zoom Outzoom out
 18 / 76 page
background image
DM9006
2-port Switch with Processor Interface
18
Preliminary datasheet
DM9006-13-DS-P01
September 1, 2009
6.1 Network Control Register (00H)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
6
LNK_X_EN
P0,WO
Link Change Status Enable
When set, it enables to report port 0 or 1 link change status function. Clearing this
bit will also clear link change status
This bit will not be affected after a software reset
5
CLR1
PH0,RW
0: REG. 01H bit 2 and 3 can be auto-cleared after read
1: REG. 01H bit 2 and 3 can be cleared by writing 1 to respected bit.
4:2
RESERVED
0,RO
Reserved
1
LBK
PH0,
RW
Loopback test Mode
All transmit packets from processor port are forward to processor port itself.
0
RST
PH0,RW
Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
5
LINK_X_ST
PH0,
W/C1
Link Change Status.
This bit is set after port 0 or 1 link changed. This bit is cleared by write 1
4
RESERVED
0,RO
Reserved
3
TX2END
PHS0,
RW/C1
TX Packet 2 Complete Status.
This bit is set after transmit completion of packet index 2
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
2
TX1END
PHS0,
RW/C1
TX Packet 1 Complete status.
This bit is set after transmit completion of packet index 1
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
1:0
RESERVED
0,RO
Reserved
6.3 TX Control Register (02H)
Bit
Name
Default
Description
7:4
RESERVED
0,RO
Reserved
3
CRC_DIS2
PHS0,RW CRC Appends Disable for Packet Index 2
2
RESERVED
0,RO
Reserved
1
CRC_DIS1
PHS0,RW CRC Appends Disable for Packet Index 1
0
TXREQ
PHS0,RW TX Request. Auto clears after transmit completely
6.4 RX Control Register (05H)
Bit
Name
Default
Description
7
HASHALL
PHS0,RW
Filter All address in Hash Table
6
RESERVED PHS0,RW
Reserved
5
RESERVED PHS0,RW
Reserved
4
DIS_CRC
PHS0,RW
Discard CRC Error Packet
3
ALL
PHS0,RW
Pass All Multicast Packets
All received packets with bit 0 is “1” of Destination Address (DA) field are accepted
and save to receive memory.
2
RESERVED PHS0,RW
Reserved


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn