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DM9006 Datasheet(PDF) 72 Page - Davicom Semiconductor, Inc. |
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DM9006 Datasheet(HTML) 72 Page - Davicom Semiconductor, Inc. |
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72 / 76 page 
DM9006 2-port Switch with Processor Interface 72 Preliminary datasheet DM9006-13-DS-P01 September 1, 2009 10.4.2 Processor I/O Read Timing IOR# SD0~15 CS#,CMD T1 T2 T3 T4 T5 T6 Symbol Parameter Min. Typ. Max. Unit T1 CS#,CMD valid to IOR# valid 5 ns T2 IOR# invalid to CS#,CMD invalid 5 ns T3 IOR# width 20 ns T4 IOR# invalid to next IOR#/IOW# valid When read DM9006 register 2 Clk *1 T4 IOR# invalid to next IOR#/IOW# valid When read DM9006 memory with F0h register 4 Clk *1 T3+T4 IOR# invalid to next IOR#/IOW# valid When read DM9006 memory with F2h register 1 Clk *1 T5 System Data(SD) Delay time 25 ns T6 IOR# invalid to System Data(SD) invalid 10 ns *1 : the Unit: clk is under the internal system clock 50MHz.(20ns). |
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