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DM9006 Datasheet(PDF) 53 Page - Davicom Semiconductor, Inc.

Part No. DM9006
Description  10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface
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Maker  DAVICOM [Davicom Semiconductor, Inc.]
Homepage  http://www.davicom.com.tw
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DM9006 Datasheet(HTML) 53 Page - Davicom Semiconductor, Inc.

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DM9006
2-port Switch with Processor Interface
Preliminary datasheet
53
DM9006-13-DS-P01
September 1, 2009
8.13 DAVICOM Specified Receive Error Counter Register (RECR) – 16H
Bit
Bit Name
Default
Description
15-0
Rcv_ Err_ Cnt
0, RO
Receive Error Counter
Receive error counter that increments upon detection of RXER.
Clean by reading this register.
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) – 17H
Bit
Bit Name
Default
Description
15-8
Reserved
0, RO
Reserved
7-0
Disconnect
Counter
0, RO
Disconnect Counter that increment upon detection of
disconnection. Clean by reading this register.
8.15 Power Saving Control Register (PSCR) – 1DH
Bit
Bit Name
Default
Description
15-12
RESERVED
0,RO
RESERVED
11
PREAMBLEX
0,RW
Preamble Saving Control
when both bit 10 and 11 of register 14H are set, the 10BASE-T
transmit preamble count is reduced.
1: 12-bit preamble is reduced.
0: 22-bit preamble is reduced.
10
AMPLITUDE
0,RW
Transmit Amplitude Control Disabled
1: when cable is unconnected with link partner, the TX amplitude is
reduced for power saving.
0: disable Transmit amplitude reduce function
9
TX_PWR
0.RW
Transmit Power Saving Control Disabled
1: when cable is unconnected with link partner, the driving current
of transmit is reduced for power saving.
0: disable transmit driving power saving function
8-0
RESERVED
0,RO
RESERVED
8.16 DAVICOM indirect DATA Register (DATA) – 1EH
Bit
Bit Name
Default
Description
15-0
DATA
0, RW
In-direct DATA register
When write, data to register that addressing by ADDR
When read, data from register that addressing by ADDR
8.17 DAVICOM indirect ADDR Register (ADDR) – 1FH
Bit
Bit Name
Default
Description
15-8
Reserved
0, RO
Reserved
3-0
ADDR
0, RW
In-direct ADDR register
1: addressing to power saving control register (same as REG
1DH)
2: reserved
3: reserved
4: addressing to TX amplitude control register


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