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DM9006 Datasheet(PDF) 50 Page - Davicom Semiconductor, Inc.

Part No. DM9006
Description  10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface
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Maker  DAVICOM [Davicom Semiconductor, Inc.]
Homepage  http://www.davicom.com.tw
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DM9006 Datasheet(HTML) 50 Page - Davicom Semiconductor, Inc.

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DM9006
2-port Switch with Processor Interface
50
Preliminary datasheet
DM9006-13-DS-P01
September 1, 2009
0
RLOUT
0, RW
Remote Loop out Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
Bit
Bit Name
Default
Description
15
100FDX
1, RO 100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it
means the operation 1 mode is a 100M full duplex mode. The software can read bit
[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when
it is not in the auto-negotiation mode
14
100HDX
1, RO 100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it
means the operation 1 mode is a 100M half duplex mode. The software can read bit
[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when
it is not in the auto-negotiation mode
13
10FDX
1, RO 10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it
means the operation 1 mode is a 10M Full Duplex mode. The software can read bit
[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when
it is not in the auto-negotiation mode
12
10HDX
1, RO 10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it
means the operation 1 mode is a 10M half duplex mode. The software can read bit
[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when
it is not in the auto-negotiation mode
11
Reserved
0, RO Reserved
Read as 0, ignore on write
10
Reserved
0,RW Reserved
9
Reserved
0,RW Reserved
8-4 PHYADR[4:0] 1, RW PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the address (bit 4). A
station management entity connected to multiple PHY entities must know the
appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be written to these
bits.
B3 B2 B1 B0
0 0 0 0
In IDLE state
0 0 0 1
Ability match
0 0 1 0
Acknowledge match
0 0 1 1
Acknowledge match fail
0 1 0 0
Consistency match
0 1 0 1
Consistency match fail
0 1 1 0
Parallel detects signal link ready
0 1 1 1
Parallel detects signal link ready fail
3-0 ANMB[3:0]
0, RO
1 0 0 0
Auto-negotiation completed successfully


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