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DM9006 Datasheet(PDF) 49 Page - Davicom Semiconductor, Inc. |
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DM9006 Datasheet(HTML) 49 Page - Davicom Semiconductor, Inc. |
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49 / 76 page 
DM9006 2-port Switch with Processor Interface Preliminary datasheet 49 DM9006-13-DS-P01 September 1, 2009 8.8 DAVICOM Specified Configuration Register (DSCR) – 10H Bit Bit Name Default Description 15 BP_4B5B 0,RW Bypass 4B5B Encoding and 5B4B Decoding 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5B and 5B4B operation 14 BP_SCR 0, RW Bypass Scrambler/Descrambler Function 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation 13 BP_ALIGN 0, RW Bypass Symbol Alignment Function 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed 0 = Normal operation 12 BP_ADPOK 0, RW BYPASS ADPOK Force signal detector (SD) active. This register is for debug only, not release to customer 1: Forced SD is OK, 0: Normal operation 11 Reserved RW Reserved Force to 0 in application 10 TX 1, RW 100BASE-TX Mode Control 1 = 100BASE-TX operation 0 = 100BASE-FX operation 9 Reserved 0, RO Reserved 8 Reserved 0, RW Reserved 7 F_LINK_100 0, RW Force Good Link in 100Mbps 1 = Force 100Mbps good link status 0 = Normal 100Mbps operation This bit is useful for diagnostic purposes 6 Reserved 0, RW Reserved Force to 0 in application. 5 COL_LED 0, RW COL LED Control (valid in PHY test mode) 4 RPDCTR-EN 1, RW Reduced Power Down Control Enable This bit is used to enable automatic reduced power down 1 = Enable automatic reduced power down 0 = Disable automatic reduced power down 3 SMRST 0, RW Reset State Machine When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed 2 MFPSC 1, RW MF Preamble Suppression Control MII frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off 1 SLEEP 0, RW Sleep Mode Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset |
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