Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

DM9006 Datasheet(PDF) 38 Page - Davicom Semiconductor, Inc.

Part No. DM9006
Description  10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface
Download  76 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  DAVICOM [Davicom Semiconductor, Inc.]
Homepage  http://www.davicom.com.tw
Logo 

DM9006 Datasheet(HTML) 38 Page - Davicom Semiconductor, Inc.

Zoom Inzoom in Zoom Outzoom out
 38 / 76 page
background image
DM9006
2-port Switch with Processor Interface
38
Preliminary datasheet
DM9006-13-DS-P01
September 1, 2009
6.61 Memory Data Write Command with Address Increment Register (F8H)
When register FFH bit 7 is “0”, register FBH value will be returned to 0000H, if 16K-byte boundary is reached.
Bit
Name
Default
Description
7:0
MWCMD
X,WO
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1, 2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
6.62 Memory Data Write Address Register (FAH)
When register FFH bit 7 is “0”, register FBH and FAH can be used as memory byte address to write internal 64K-byte
memory.
When register FFH bit 7 is “1”, register FBH and FAH are reserved. The processor port transmit memory address is generated
by DM9006 automatically.
Bit
Name
Default
Description
7:0
MDWAL
PHS0,RW Memory Data Write_ address Low Byte[7:0]
6.63 Memory Data Write Address Register (FBH)
Bit
Name
Default
Description
7:0
MDWAH
PHS0,RW Memory Data Write Byte Address High Byte[15:8]
6.64 TX Packet Length Registers (FCH~FDH)
Bit
Name
Default
Description
7:0
TXPLH
PHS0,RW TX Packet Length High byte
7:0
TXPLL
PHS0,RW TX Packet Length Low byte
6.65 Interrupt Status Register (FEH)
Bit
Name
Default
Description
7
IOMODE
T0, RO
Width Processor Data Bus
0: 16-bit mode
1: 8-bit mode
6
RESERVED
PHS0,RO
Reserved
5
LNKCHG
PHS0,RW/C1
Link Status Change of port 0 or 1
4
CNT_ERR
PHS0,RW/C1
Memory Management error
3
ROO
PHS0,RW/C1
Receive Overflow Counter Overflow
2
ROS
PHS0,RW/C1
Receive Overflow
1
PT
PHS0,RW/C1
Packet Transmitted
0
PR
PHS0,RW/C1
Packet Received
6.66 Interrupt Mask Register (FFH)
Bit
Name
Default
Description
7
TXRX_EN
PHS0,RW
Enable the SRAM read/write pointer used as transmit /receive address.
6
RESERVED
P0,RO
Reserved
5
LNKCHGI
PHS0,RW
Enable Link Status Change of port 0 or 1Interrupt
4
CNT_ERR
PHS0,RW/C1
Enable Memory Management error interrupt
3
ROOI
PHS0,RW
Enable Receive Overflow Counter Overflow Interrupt
2
ROI
PHS0,RW
Enable Receive Overflow Interrupt
1
PTI
PHS0,RW
Enable Packet Transmitted Interrupt
0
PRI
PHS0,RW
Enable Packet Received Interrupt


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn