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DM9006 Datasheet(PDF) 37 Page - Davicom Semiconductor, Inc.

Part No. DM9006
Description  10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface
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Maker  DAVICOM [Davicom Semiconductor, Inc.]
Homepage  http://www.davicom.com.tw
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DM9006 Datasheet(HTML) 37 Page - Davicom Semiconductor, Inc.

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DM9006
2-port Switch with Processor Interface
Preliminary datasheet
37
DM9006-13-DS-P01
September 1, 2009
6.55 VLAN Priority Map Registers (D0H~D1H)
Define the 3-bit of priority field VALN mapping to 2-bit priority queue number.
Reg. D0H:
Bit
Name
Default
Description
7:6
TAG3
PHE1,RW VLAN priority tag value = 03H
5:4
TAG2
PHE1,RW VLAN priority tag value = 02H
3:2
TAG1
PHE0,RW VLAN priority tag value = 01H
1:0
TAG0
PHE0,RW VLAN priority tag value = 00H
Reg. D1H:
Bit
Name
Default
Description
7:6
TAG7
PHE3,RW VLAN priority tag value = 07H
5:4
TAG6
PHE3,RW VLAN priority tag value = 06H
3:2
TAG5
PHE2,RW VLAN priority tag value = 05H
1:0
TAG4
PHE2,RW VLAN priority tag value = 04H
6.56 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
7:0
MRCMDX
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged. And the DM9006 starts to pre-fetch the SRAM data
to internal data buffers.
6.57 Memory Data Read Command with Address Increment Register (F2H)
When register FFH bit 7 is “0”, register F5H value will be returned to 0000H, if 16K-byte boundary is reached.
When register FFH bit 7 is “1”, register F5H value will be returned to 0000H, if processor port receive memory byte boundary
address RX memory size, defined in register 3FH with default 1F00H, is reached.
Bit
Name
Default
Description
7:0
MRCMD
X,RO
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
6.58 Memory Data Read Address Register (F4H)
When register FFH bit 7 is “0”, register F5H and F4H can be used as memory byte address to read internal 64K-byte memory.
When register FFH bit 7 is “1”, register F5H and F4H can be used as processor port receive memory byte address with
memory space range from 0 to (RX memory size - 1), defined in register 3FH with default 1EFFH.
Bit
Name
Default
Description
7:0
MDRAL
PHS0,RW Memory Data Read Address Low Byte[7:0]
6.59 Memory Data Read Address Register (F5H)
Bit
Name
Default
Description
7:0
MDRAH50
PHS0,RW Memory Data Read Byte Address High Byte[15:8]
6.60 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
Description
7:0
MWCMDX
X,WO
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged


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