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DM9000BEP Datasheet(PDF) 31 Page - Davicom Semiconductor, Inc. |
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DM9000BEP Datasheet(HTML) 31 Page - Davicom Semiconductor, Inc. |
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31 / 63 page  DM9000B Ethernet Controller with General Processor Interface Final 31 Version: DM9000B-13-DS-F03 March 5, 2012 6.42 Memory data write command with address increment Register (F8H) Bit Name Default Description 7:0 MWCMD X,WO Write Data to TX SRAM After the write of this command, the write pointer is increased by 1 or 2, depends on the operator mode. (8-bit or 16-bit respectively) 6.43 Memory data write address Register (FAH~FBH) Bit Name Default Description 7:0 MDWAH PS0,RW Memory Data Write_ address High Byte 7:0 MDWAL PS0,RW Memory Data Write_ address Low Byte 6.44 TX Packet Length Register (FCH~FDH) Bit Name Default Description 7:0 TXPLH X,R/W TX Packet Length High byte 7:0 TXPLL X,,R/W TX Packet Length Low byte 6.45 Interrupt Status Register (FEH) Bit Name Default Description 7 IOMODE T0, RO 0 : 16-bit mode 1: 8-bit mode 6 RESERVED RO Reserved 5 LNKCHG PS0,RW/C1 Link Status Change 1: Affirmative 0: Negative 4 UDRUN PS0,RW/C1 Transmit Under-run 1: Affirmative 0: Negative 3 ROO PS0,RW/C1 Receive Overflow Counter Overflow 1: Affirmative 0: Negative 2 ROS PS0,RW/C1 Receive Overflow 1: Affirmative 0: Negative 1 PT PS0,RW/C1 Packet Transmitted 1: Affirmative 0: Negative 0 PR PS0,RW/C1 Packet Received 1: Affirmative 0: Negative 6.46 Interrupt Mask Register (FFH) Bit Name Default Description |
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