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DM9000B Datasheet(PDF) 14 Page - Davicom Semiconductor, Inc. |
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DM9000B Datasheet(HTML) 14 Page - Davicom Semiconductor, Inc. |
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14 / 63 page  DM9000B Ethernet Controller with General Processor Interface Final 14 Version: DM9000B-13-DS-F03 March 5, 2012 RSCCR Resume System Clock Control Register 51H XXH MRCMDX Memory Data Pre-Fetch Read Command Without Address Increment Register F0H XXH MRCMDX1 Memory Data Read Command With Address Increment Register F1H XXH MRCMD Memory Data Read Command With Address Increment Register F2H XXH MRRL Memory Data Read_ address Register Low Byte F4H 00H MRRH Memory Data Read_ address Register High Byte F5H 00H MWCMDX Memory Data Write Command Without Address Increment Register F6H XXH MWCMD Memory Data Write Command With Address Increment Register F8H XXH MWRL Memory Data Write_ address Register Low Byte FAH 00H MWRH Memory Data Write _ address Register High Byte FBH 00H TXPLL TX Packet Length Low Byte Register FCH XXH TXPLH TX Packet Length High Byte Register FDH XXH ISR Interrupt Status Register FEH 00H IMR Interrupt Mask Register FFH 00H Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value P = power on reset default value S = software reset default value E = default value from EEPROM T = default value from strap pin <Access Type>: RO = Read only RW = Read/Write R/C = Read and Clear RW/C1=Read/Write and Cleared by write 1 WO = Write only Reserved bits are shaded and should be written with 0. Reserved bits are undefined on read access. *If Register 1FH bit 0 is updated from ‘1’ to ‘0’, the all Registers can not be accessed within 1ms. 6.1 Network Control Register (00H) Bit Name Default Description 7 RESERVED P0,RW Reserved 6 WAKEEN P0,RW When set, it enables the wakeup function. Clearing this bit will also clears all wakeup event status This bit will not be affected after a software reset 0: Enable 1: Disable 5 RESERVED 0,RO Reserved 4 FCOL PS0,RW 1: Force Collision Mode, used for testing 0: DISABLE 3 FDX PS0,RO Duplex mode of the internal PHY. 1: Full-duplex 0: half-duplex |
Similar Part No. - DM9000B |
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Similar Description - DM9000B |
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