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DS1308

RTC and RAM Address Map

Table 3 shows the address map for the RTC and RAM

registers. The RTC registers and control register are

located in address locations 00h–07h. The RAM regis-

ters are located in address locations 08h–3Fh. During a

multibyte access, when the register pointer reaches 3Fh

(the end of RAM space) it wraps around to location 00h

register pointer incrementing to location 00h, the current

time and date is transferred to a second set of registers.

The time and date in the secondary registers are read in

a multibyte data transfer, while the clock continues to run.

This eliminates the need to re-read the registers in case

of an update of the main registers during a read.

Clock and Calendar

The time and calendar information is obtained by reading

the appropriate register bytes. The time and calendar are

set or initialized by writing the appropriate register bytes.

The contents of the time and calendar registers are in the

BCD format. Bit 7 of Register 0 is the clock halt (CH) bit.

When this bit is set to 1, the oscillator is disabled. When

cleared to 0, the oscillator is enabled. The clock can

be halted whenever the timekeeping functions are not

The day-of-week register increments at midnight. Values

that correspond to the day of week are user-defined

but must be sequential (i.e., if 1 equals Sunday, then

2 equals Monday, and so on). Illogical time and date

entries result in undefined operation.

When reading or writing the time and date registers,

secondary (user) buffers are used to prevent errors when

the internal registers update. When reading the time and

date registers, the user buffers are synchronized to the

internal registers on any START and when the register

pointer rolls over to zero. The countdown chain is reset

whenever the seconds register is written. Write transfers

occur on the acknowledge from the DS1308. Once the

countdown chain is reset, to avoid rollover issues the

remaining time and date registers must be written within

1 second. The 1Hz square-wave output, if enabled,

transitions high 500ms after the seconds data transfer,

provided the oscillator is already running.

The DS1308 runs in either 12-hour or 24-hour mode.

Bit 6 of the hours register is defined as the 12-hour or

24-hour mode-select bit. When high, the 12-hour mode

is selected. In the 12-hour mode, bit 5 is the AM/PM bit,

with logic high being PM. In the 24-hour mode, bit 5 is the

20-hour bit (20–23 hours). If the 12/24-hour mode select

is changed, the hours register must be re-initialized to

the new format.

Table 3. RTC and RAM Address Map

Note: Bits listed as “0” always read as a 0.

ADDRESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

FUNCTION

RANGE

00h

CH

10 Seconds

Seconds

Seconds

00–59

01h

0

10 Minutes

Minutes

Minutes

00–59

02h

0

12/24

AM/PM

10 Hour

Hour

Hours

1–12 +AM/

PM

00–23

20 Hour

03h

0

0

0

0

0

Day

Day

1–7

04h

0

0

10 Date

Date

Date

01–31

05h

0

0

0

10

Month

Month

Month

01–12

06h

10 Year

Year

Year

00–99

07h

OUT

ECLK

OSF

SQWE

LOS

BBCLK

RS1

RS0

Control

08h–3Fh

RAM 56 x 8

00h–FFh