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ADXL362 Datasheet(PDF) 32 Page - Analog Devices |
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ADXL362 Datasheet(HTML) 32 Page - Analog Devices |
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32 / 40 page  ADXL362 Preliminary Technical Data Rev. PrB | Page 32 of 40 Stream Mode In Stream Mode, the FIFO always contains the most recent data. The oldest sample is discarded if space is needed to make room for a newer sample. Stream Mode is useful for unburdening a host processor. The processor can tend to other tasks while data is collected in the FIFO. When the FIFO fills to a certain number of samples (specified by FIFO_SAMPLES), it triggers a Watermark Interrupt. At this point, the host processor can read the contents of the entire FIFO, and then return to its other tasks as the FIFO fills again. The FIFO is placed into Stream Mode by setting the FIFO_MODE bits in the FIFO_CONTROL register (address 0x28) to binary value 0b10. Triggered Mode In Triggered Mode, the FIFO saves samples surrounding an Activity detection event. The operation is similar to a One-time Run trigger on an oscilloscope. The FIFO is placed into Triggered Mode by setting the FIFO_MODE bits in the FIFO_CONTROL register (address 0x28) to binary value 0b11. Configuration The FIFO is configured via registers 0x28 and 0x29. Settings are described in detail on page 25. Retrieving Data from FIFO FIFO data is read by issuing a FIFO read command, described in the SPI Commands section. Data is formatted as a 16-bit value as represented in Table 17. When reading data, the least-significant byte (Bits B7:B0) is read first, followed by the most-significant byte (Bits B15:B8). Bits B11:B0 represent the 12-bit, two’s complement acceleration or temperature data. Bits B13:B12 are sign extension bits, and bits B15:B14 indicate the type of data, as indicated in Table 17. Table 17. FIFO Buffer Data Format B7 B6 B5 B4 B3 B2 B1 B0 Data LSB B15 B14 B13 B12 B11 B10 B9 B8 Data Type: 00: x-axis 01: y-axis 10: z-axis 11: temp Sign Extension MSB Data Due to the 16-bit data format, it is required that data be read from the FIFO two bytes at a time. If a multi-byte read is performed, the number of bytes read should always be an even number. Multi-byte reads of FIFO data can be performed with no limit on the number of bytes read. If additional bytes are read after the FIFO is empty, the data in them will be 0x00. As each sample set is acquired, it is written into the FIFO in the following order: <X-Axis> <Y-Axis > <Z-Axis > <Temperature> [optional] This pattern repeats until the FIFO is full, at which point the behavior depends on the FIFO Mode (see the FIFO section on page 31). If the FIFO has insufficient space for four data entries (or three entries if temperature is not being stored), then an incomplete sample set may be stored. FIFO data is output on a per datum basis: as each data item is read, the same amount of space is freed up in the stack. Again, this may lead to incomplete sample sets being present in the FIFO. For additional system-level FIFO applications, refer to application note AN-1025, Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc. Digital Accelerometers. INTERRUPTS Several of the built-in functions of the ADXL362 can trigger interrupts to alert the host processor of certain status conditions. Functionality of these interrupts is described in this section. Interrupt Pins Interrupts may be mapped to either (or both) of two designated output pins, INT1 and INT2, by setting the appropriate bits in the INTMAP1 and INTMAP2 registers, respectively. All functions can be used simultaneously. If multiple interrupts are mapped to one pin, the OR combination of the interrupts determines the status of the pin. If no functions are mapped to an interrupt pin, that pin is automatically configured to a high-impedance (high-Z) state. The pins are placed in this state upon a reset as well. When a certain status condition is detected, the pin that condition is mapped to is activated. The configuration of the pin is active high by default, so that when it is activated the pin goes high. However, this configuration can be switched to active low by setting the INT_LOW pin in the appropriate INTMAP register. The INT pins may be connected to the interrupt input of a host processor and interrupts responded to with an interrupt routine. Because multiple functions can be mapped to the same |
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