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IRF7811 Datasheet(PDF) 27 Page - Analog Devices
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IRF7811 Datasheet(HTML) 27 Page - Analog Devices
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Rev. A | Page 27 of 40
The amount of loss through the body diode of the low-side
MOSFET during the anti overlap state is given by the following
is the body conduction time (refer to Figure 84 for
dead time periods).
is the period per switching cycle.
is the forward drop of the body diode during conduction.
(Refer to the selected external MOSFET data sheet for more
information about the V
Figure 84. Body Diode Conduction Time vs. Low Voltage Input (V
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1878/ADP1879
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
If bulk electrolytic capacitors are used, it is recommended to use
multilayered ceramic capacitors (MLCC) in parallel due to their
low ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across the
drain of the high-side MOSFET and the source terminal of the
low-side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
high-side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
is usually 1% of the minimum voltage input.
is the maximum load current.
ESR is the equivalent series resistance rating of the input capacitor.
into the charge balance equation to
calculate the minimum input capacitor requirement gives
where D = 50%.
The ADP1878/ADP1879 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current and be subjected to high ambient
temperature, the selection of external high- and low-side MOSFETs
must be associated with careful thermal consideration to not
exceed the maximum allowable junction temperature of 125°C.
To avoid permanent or irreparable damage, if the junction temper-
ature reaches or exceeds 155°C, the part enters thermal shutdown,
turning off both external MOSFETs, and is not reenabled until
the junction temperature cools to 140°C (see the On-Board Low
Dropout (LDO) Regulator section).
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1878/ADP1879 employ an
on-board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs, adds another element of
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