Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

IRF7811 Datasheet(PDF) 26 Page - Analog Devices

Part No. IRF7811
Description  Synchronous Buck Controller
Download  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

IRF7811 Datasheet(HTML) 26 Page - Analog Devices

Back Button IRF7811 Datasheet HTML 22Page - Analog Devices IRF7811 Datasheet HTML 23Page - Analog Devices IRF7811 Datasheet HTML 24Page - Analog Devices IRF7811 Datasheet HTML 25Page - Analog Devices IRF7811 Datasheet HTML 26Page - Analog Devices IRF7811 Datasheet HTML 27Page - Analog Devices IRF7811 Datasheet HTML 28Page - Analog Devices IRF7811 Datasheet HTML 29Page - Analog Devices IRF7811 Datasheet HTML 30Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 26 / 40 page
background image
ADP1878/ADP1879
Data Sheet
Rev. A | Page 26 of 40
EFFICIENCY CONSIDERATION
An important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents of up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
VGS (TH) is the MOSFET voltage applied between the gate
and the source that starts channel conduction.
RDS (ON) is the on resistance of the MOSFET during channel
conduction.
QG is the total gate charge.
CN1 is the input capacitance of the high-side switch.
CN2 is the input capacitance of the low-side switch.
The following are the losses experienced through the external
component during normal switching operation:
Channel conduction loss (both of the MOSFETs).
MOSFET driver loss.
MOSFET switching loss.
Body diode conduction loss (low-side MOSFET).
Inductor loss (copper and core loss).
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the high-side MOSFET is directly proportional
to the duty cycle (D) for each switching period, and the power
loss through the low-side MOSFET is directly proportional to
1 − D for each switching period. The selection of MOSFETs is
governed by the maximum dc load current that the converter is
expected to deliver. In particular, the selection of the low-side
MOSFET is dictated by the maximum load current because a
typical high current application employs duty cycles of less than
50%. Therefore, the low-side MOSFET is in the on state for
most of the switching period.
1, 2
1
1
2
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The con-
tributing factors are the dc current flowing through the driver
during operation and the QGATE parameter of the external MOSFETs.
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VREG ×
(fSWClowerFETVREG + IBIAS)]
where:
CupperFET is the input gate capacitance of the high-side MOSFET.
ClowerFET is the input gate capacitance of the low-side MOSFET.
IBIAS is the dc current flowing into the high- and low-side drivers.
VDR is the driver bias voltage (that is, the low input voltage (VREG)
minus the rectifier drop (see Figure 83)).
VREG is the bias voltage.
Figure 83. Internal Rectifier Voltage Drop vs. Switching Frequency
MOSFET Switching Loss
The SW node transitions due to the switching activities of the
high- and low-side MOSFETs. This causes removal and reple-
nishing of charge to and from the gate oxide layer of the MOSFET,
as well as to and from the parasitic capacitance associated with
the gate oxide edge overlap and the drain and source terminals.
The current that enters and exits these charge paths presents
additional loss during these transition times. This can be approxi-
mately quantified by using the following equation, which represents
the time in which charge enters and exits these capacitive regions:
tSW-TRANS = RGATE × CTOTAL
where:
CTOTAL is the CGD + CGS of the external MOSFET.
RGATE is the gate input resistance of the external MOSFET.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
-TRANS
2
or
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
Body Diode Conduction Loss
The ADP1878/ADP1879 employ anti cross conduction circuitry
that prevents the high- and low-side MOSFETs from conducting
current simultaneously. This overlap control is beneficial, avoiding
large current flow that may lead to irreparable damage to the
external components of the power stage. However, this blanking
period comes with the trade-off of a diode conduction loss
occurring immediately after the MOSFETs change states and
continuing well into idle mode.
800
720
640
560
480
400
320
240
160
80
300
1000
900
800
700
600
500
400
SWITCHING FREQUENCY (kHz)
+125°C
+25°C
–40°C
VREG = 2.7V
VREG = 3.6V
VREG = 5.5V


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn