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ADP5061 Datasheet(PDF) 7 Page - Analog Devices |
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ADP5061 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 44 page  Data Sheet ADP5061 Rev. 0 | Page 7 of 44 ABSOLUTE MAXIMUM RATINGS Table 4. Absolute Maximum Ratings Parameter Rating VIN1, VIN2, VIN3 to AGND –0.5 V to +20 V All Other Pins to AGND –0.3 V to +6 V Continuous Drain Current, Battery Supple- mentary Mode, from ISO_Bx to ISO_Sx 2.1 A Storage Temperature Range –65°C to +150°C Operating Junction Temperature Range –40°C to +125°C Soldering Conditions JEDEC J-STD-020 THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for surface- mount packages. Table 5. Thermal Resistance Package Type θJA θJC θJB Unit 20-Lead WLCSP1 46.8 0.7 9.2 °C/W 1 5 × 4 array, 0.5 mm pitch (2.6 mm × 2.0 mm); based on a JEDEC 2S2P, 4-layer board with 0 m/sec airflow. Maximum Power Dissipation The maximum safe power dissipation in the ADP5061 package is limited by the associated rise in junction temperature (TJ) on the die. At a die temperature of approximately 150°C (the glass transition temperature), the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, thereby perma- nently shifting the parametric performance of the ADP5061. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices, potentially causing failure. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. |
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