ADN4696EBRZ datasheet(14/20 Pages) AD

Part #	ADN4696EBRZ

Description	3.3 V, 200 Mbps, Half- and Full-Duplex

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14 / 20 page

ADN4691E/ADN4693E/ADN4696E/ADN4697E

Data Sheet

Rev. A | Page 14 of 20

THEORY OF OPERATION

The ADN4691E/ADN4693E/ADN4696E/ADN4697E are

transceivers for transmitting and receiving multipoint, low

voltage differential signaling (M-LVDS) at high speed (data

rates up to 200 Mbps). Each device has a differential line driver

and a differential line receiver, allowing each device to send and

receive data.

Multipoint LVDS expands on the established LVDS low voltage

differential signaling method by allowing bidirectional commu-

nication between more than two nodes. Up to 32 nodes can be

connected on an M-LVDS bus.

HALF-DUPLEX/FULL-DUPLEX OPERATION

Half-duplex operation allows a transceiver to transmit or

receive, but not both at the same time. However, with full-

duplex operation, a transceiver can transmit and receive

simultaneously. The ADN4691E/ADN4696E are half-duplex

devices in which the driver and the receiver share differential

bus terminals. The ADN4693E/ADN4697E are full-duplex

devices that have dedicated driver output and receiver input

pins. Figure 37 and Figure 38 show typical half- and full-duplex

bus topologies, respectively, for M-LVDS.

THREE-STATE BUS CONNECTION

The outputs of the device can be placed in a high impedance

state by disabling the driver or receiver. This allows several

driver outputs to be connected to a single M-LVDS bus. Note

that, on each bus line, only one driver can be enabled at a time,

but many receivers can be enabled at the same time.

The driver can be enabled or disabled using the driver enable

pin (DE). DE enables the driver outputs when taken high; when

taken low, DE puts the driver outputs into a high impedance state.

Similarly, an active low receiver enable pin (RE) controls the

receiver. Taking RE low enables the receiver, whereas taking it

high puts the receiver outputs into a high impedance state.

Truth tables for driver and receiver output states under various

conditions are shown in Table 10, Table 11, Table 12 and

Table 13.

TRUTH TABLES

Table 9. Truth Table Abbreviations

Abbreviation

Description

H

High level

L

Low level

X

Don’t care

I

Indeterminate

Z

High impedance (off )

NC

Disconnected

Driver, Half Duplex (ADN4691E/ADN4696E)

Table 10. Transmitting (See Table 9 for Abbreviations)

Inputs

Outputs

Power

DE

DI

A

B

Yes

H

L

Yes

H

L

H

Yes

H

NC

L

H

Yes

L

X

Z

Yes

NC

X

Z

≤1.5 V

X

Z

Driver, Full Duplex (ADN4693E/ADN4697E)

Table 11. Transmitting (See Table 9 for Abbreviations)

Inputs

Outputs

Power

DE

DI

Y

Z

Yes

H

L

Yes

H

L

H

Yes

H

NC

L

H

Yes

L

X

Z

Yes

NC

X

Z

≤1.5 V

X

Z

Type 1 Receiver (ADN4691E/ADN4693E)

Table 12. Receiving (see Table 9 for Abbreviations)

Inputs

Output

Power

A − B

RE

RO

Yes

≥50 mV

L

H

Yes

≤−50 mV

L

Yes

−50 mV < A − B < 50 mV

L

I

Yes

NC

L

I

Yes

X

H

Z

Yes

X

NC

Z

No

X

Z

Type 2 Receiver (ADN4696E/ADN4697E)

Table 13. Receiving (See Table 9 for Abbreviations)

Inputs

Output

Power

A − B

RE

RO

Yes

≥150 mV

L

H

Yes

≤50 mV

L

Yes

50 mV < A − B < 150 mV

L

I

Yes

NC

L

Yes

X

H

Z

Yes

X

NC

Z

No

X

Z

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