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ADP1047DC1-EVALZ Datasheet(PDF) 48 Page - Analog Devices |
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ADP1047DC1-EVALZ Datasheet(HTML) 48 Page - Analog Devices |
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48 / 84 page  ADP1047/ADP1048 Data Sheet Rev. 0 | Page 48 of 84 Bits Bit Name R/W Description [5:3] Retry setting R/W Number of retry attempts following a fault condition. If the fault persists after the programmed number of attempts, the output is disabled and remains off until the fault is cleared. A fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. The time between restart attempts is specified by Delay Time 2 (Bits[2:0]). Bit 5 Bit 4 Bit 3 Number of Retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 Infinite [2:0] Delay times R/W Delay Time 1 is the delay before the device disables the output after a fault condition is detected. Delay Time 2 is the time between restart attempts. Bit 2 Bit 1 Bit 0 Delay Time 1 Delay Time 2 0 0 0 10 ms 252 ms 0 0 1 20 ms 558 ms 0 1 0 40 ms 924 ms 0 1 1 80 ms 1260 ms 1 0 0 160 ms 1596 ms 1 0 1 320 ms 1932 ms 1 1 0 640 ms 2268 ms 1 1 1 1280 ms 2604 ms VOUT_OV_WARN_LIMIT REGISTER This register sets the accurate overvoltage threshold measured at the PFC output that causes an overvoltage warning condition. Table 29. Register 0x42—VOUT_OV_WARN_LIMIT Bits Bit Name R/W Description [15:11] Exponent R Return the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent (N) is set in the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N). VOUT_UV_WARN_LIMIT REGISTER This register sets the undervoltage threshold measured at the PFC output that causes an undervoltage warning condition. Table 30. Register 0x43—VOUT_UV_WARN_LIMIT Bits Bit Name R/W Description [15:11] Exponent R Return the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent (N) is set in the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N). VOUT_UV_FAULT_LIMIT REGISTER This register sets the undervoltage threshold measured at the PFC output that causes an undervoltage fault condition. Table 31. Register 0x44—VOUT_UV_FAULT_LIMIT Bits Bit Name R/W Description [15:11] Exponent R Return the exponent (N) used in VOUT linear mode format (X = Y × 2N). The exponent (N) is set in the VOUT_MODE register (Register 0x20, Bits[2:0]). The exponent is in twos complement format. [10:8] High bits R/W Mantissa high bits (Y[10:8]) used in VOUT linear mode format (X = Y × 2N). [7:0] Low byte R/W Mantissa low byte (Y[7:0]) used in VOUT linear mode format (X = Y × 2N). |
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