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ADN4697E Datasheet(PDF) 5 Page - Analog Devices |
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ADN4697E Datasheet(HTML) 5 Page - Analog Devices |
5 / 20 page Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E Rev. A | Page 5 of 20 Table 4. Test Voltages for Type 2 Receiver Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output VA (V) VB (V) VID (V) VIC (V) RO 2.4 0 2.4 1.2 H 0 2.4 −2.4 1.2 L 3.475 3.325 0.15 3.4 H 3.425 3.375 0.05 3.4 L −0.925 −1.075 0.15 −1 H −0.975 −1.025 0.05 −1 L TIMING SPECIFICATIONS VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1 Table 5. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 100 Mbps Propagation Delay tPLH, tPHL 2 2.5 3.5 ns See Figure 23, Figure 26 Differential Output Rise/Fall Time tR, tF 2 2.6 3.2 ns See Figure 23, Figure 26 Pulse Skew |tPHL − tPLH| tSK 30 150 ps See Figure 23, Figure 26 Part-to-Part Skew tSK(PP) 0.9 ns See Figure 23, Figure 26 Period Jitter, rms (One Standard Deviation)2 tJ(PER) 2 3 ps 50 MHz clock input3 (see Figure 25) Peak-to-Peak Jitter2, 4 tJ(PP) 150 ps 100 Mbps 215 − 1 PRBS input5 (see Figure 28) Disable Time from High Level tPHZ 4 7 ns See Figure 24, Figure 27 Disable Time from Low Level tPLZ 4 7 ns See Figure 24, Figure 27 Enable Time to High Level tPZH 4 7 ns See Figure 24, Figure 27 Enable Time to Low Level tPZL 4 7 ns See Figure 24, Figure 27 RECEIVER Propagation Delay tRPLH, tRPHL 2 6 ns CL = 15 pF (see Figure 29, Figure 32) Rise/Fall Time tR, tF 1 2.3 ns CL = 15 pF (see Figure 29, Figure 32) Pulse Skew |tRPHL – tRPLH| CL = 15 pF (see Figure 29, Figure 32) Type 1 Receiver (ADN4690E, ADN4692E) tSK 100 300 ps Type 2 Receiver (ADN4694E, ADN4695E) tSK 300 500 ps Part-to-Part Skew6 tSK(PP) 1 ns CL = 15 pF (see Figure 29, Figure 32) Period Jitter, rms (One Standard Deviation)2 tJ(PER) 4 7 ps 50 MHz clock input3 (see Figure 31) Peak-to-Peak Jitter2, 4 100 Mbps 215 − 1 PRBS input5 (see Figure 34) Type 1 Receiver (ADN4690E, ADN4692E) tJ(PP) 200 700 ps Type 2 Receiver (ADN4694E, ADN4695E) tJ(PP) 225 800 ps Disable Time from High Level tRPHZ 6 10 ns See Figure 30, Figure 33 Disable Time from Low Level tRPLZ 6 10 ns See Figure 30, Figure 33 Enable Time to High Level tRPZH 10 15 ns See Figure 30, Figure 33 Enable Time to Low Level tRPZL 10 15 ns See Figure 30, Figure 33 1 All typical values are given for VCC = 3.3 V and TA = 25°C. 2 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter. 3 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples. 4 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK). 5 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples. 6 HP4194A impedance analyzer or equivalent. |
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