 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADP1046ACPZ-RL Datasheet(PDF) 80 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADP1046ACPZ-RL Datasheet(HTML) 80 Page - Analog Devices |
|
|
80 / 96 page  ADP1046 Data Sheet Rev. 0 | Page 80 of 96 Table 112. Register 0x70—Dead Time Configuration Bits Bit Name R/W Description [7:6] Averaging period R/W These bits specify the averaging period for the CS1 current used to set the adaptive dead time. It is recommended that the averaging time be set to a value much greater than any transient condition. Bit 7 Bit 6 Averaging Period 0 0 2.5 ms 0 1 1.2 ms 1 0 600 μs 1 1 Reserved [5:3] Update rate R/W The ADT algorithm adjusts the dead time in steps of 5 ns. These bits are used to program the number of PWM switching cycles between each step. The number is calculated as 2N + 1 where N is the 3-bit value specified by these bits. If N = 6 (110), each PWM edge is adjusted by 5 ns every 26 + 1 = 65 switching cycles. [2:0] Multiplier R/W These bits specify the programming step for Register 0x69 to Register 0x6F, Bits[6:4] and Bits[2:0]. Bit 2 Bit 1 Bit 0 Multiplier 0 0 0 5 0 0 1 10 0 1 0 15 0 1 1 20 1 0 0 25 1 0 1 30 1 1 0 35 1 1 1 40 SOFT START FILTER PROGRAMMING REGISTERS Table 113. Register 0x71—Soft Start Digital Filter LF Gain Setting Bits Bit Name R/W Description [7:0] LF gain setting R/W This register determines the low frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. Table 114. Register 0x72—Soft Start Digital Filter Zero Setting Bits Bit Name R/W Description [7:0] Zero setting R/W This register determines the position of the final zero. See Figure 57. Table 115. Register 0x73—Soft Start Digital Filter Pole Setting Bits Bit Name R/W Description [7:0] Pole location R/W This register determines the position of the final pole. See Figure 57. Table 116. Register 0x74—Soft Start Digital Filter HF Gain Setting Bits Bit Name R/W Description [7:0] HF gain setting R/W This register determines the high frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. |
Similar Part No. - ADP1046ACPZ-RL |
|
Similar Description - ADP1046ACPZ-RL |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
