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ADN4692E Datasheet(PDF) 13 Page - Analog Devices

Part No. ADN4692E
Description  3.3 V, 200 Mbps, Half- and Full-Duplex
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADN4692E Datasheet(HTML) 13 Page - Analog Devices

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Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. A | Page 13 of 20
RECEIVER TIMING MEASUREMENTS
A
NOTES
1. CL IS 20%, CERAMIC, SURFACE MOUNT, AND INCLUDES
PROBE/STRAY CAPACITANCE < 2cm FROM DUT.
VOUT
CL
15pF
B
RO
RE
VID
Figure 30. Receiver Timing Measurement
A
1.4V
1.0V
1.2V
RE INPUT
NOTES
1. CL IS 20% AND INCLUDES PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
2. RL IS 1% METAL FILM, SURFACE MOUNT, <2cm FROM DUT.
VOUT
CL
15pF
RL
499Ω
B
RO
RE
VTEST
Figure 31. Receiver Enable/Disable Time
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
100MHz; 50% ± 1% DUTY CYCLE.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
VOH
VOL
0V
1/f0
INPUT
(VA – VB)
0.5VCC
0.5VCC
0.5VCC
0.5VCC
1/f0
OUTPUT
(IDEAL)
VOH
VOL
OUTPUT
(ACTUAL)
tc(n)
tJ(PER) = |tc(n) – 1f0|
Figure 32. Receiver Period Jitter Characteristics
NOTES
1. INPUT PULSE GENERATOR: 50MHz; 50% ± 5% DUTY CYCLE; tR, tF ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
tRPHL
VA
0.5VCC
0.5VCC
VB
VOH
VOL
VID
VOUT
0V
90%
10%
90%
10%
0V
tF
tRPLH
tR
Figure 33. Receiver Propagation and Rise/Fall Times
0.5VCC
0.5VCC
VCC
0V
VCC
0V
VOL
VOH
0.5VCC
0.5VCC
VOH – 0.5V
RE INPUT
(VTEST = VCC)
(A = 1V)
VOUT
VOUT
(VTEST = 0V)
(A = 1.4V)
tRPZH
tRPZL
VOL + 0.5V
tRPHZ
tRPLZ
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUTY CYCLE;
tR, tF ≤ 1ns.
Figure 34. Receiver Enable/Disable Times
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
200Mbps; 215 – 1PRBS.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
VOH
VOL
VA
VB
OUTPUT
INPUT
(PRBS)
tJ(PP)
0.5VCC
0.5VCC
Figure 35. Receiver Peak-to-Peak Jitter Characteristics


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