Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADN4692E Datasheet(PDF) 12 Page - Analog Devices

Part No. ADN4692E
Description  3.3 V, 200 Mbps, Half- and Full-Duplex
Download  20 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

ADN4692E Datasheet(HTML) 12 Page - Analog Devices

Zoom Inzoom in Zoom Outzoom out
 12 / 20 page
background image
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Data Sheet
Rev. A | Page 12 of 20
DRIVER TIMING MEASUREMENTS
DI
NOTES
1. C1, C2, AND C3 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE LESS THAN 2cm FROM DUT.
2. R1 IS 1%, METAL FILM, SURFACE MOUNT,
LESS THAN 2cm FROM DUT.
OUT
C1
1pF
C3
0.5pF
C2
1pF
A/Y
B/Z
R1
50Ω
Figure 24. Driver Timing Measurement
DI
DE
S1
VCC
NOTES
1. C1, C2, C3, AND C4 ARE 20% AND INCLUDE PROBE/STRAY
CAPACITANCE LESS THAN 2cm FROM DUT.
2. R1 AND R2 ARE 1%, METAL FILM, SURFACE MOUNT,
LESS THAN 2cm FROM DUT.
R1
24.9Ω
C1
1pF
C2
1pF
C3
2.5pF
R2
24.9Ω
A/Y
B/Z
C4
0.5pF OUT
Figure 25. Driver Enable/Disable Time
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
100MHz; 50% ± 1% DUTY CYCLE.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
VCC/2
VCC/2
VCC
0V
1/f0
INPUT
(CLOCK)
0V
0V
1/f0
OUTPUT
VA – VB
OR
VY – VZ
(IDEAL)
0V
0V
tc(n)
tJ(PER) = |tc(n) – 1/f0|
OUTPUT
VA – VB
OR
VY – VZ
(ACTUAL )
Figure 26. Driver Period Jitter Characteristics
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUT Y CYCLE;
tR, tF ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
tPLH
tR
tF
tPHL
VCC
VSS
VPH
VPL
0% VSS
10% VSS
90% VSS
0V
0V
0V
OUT
DI
10% VSS
90% VSS
0.5VCC
0.5VCC
Figure 27. Driver Propagation, Rise/Fall Times and Voltage Overshoot
0.5VCC
0.5VCC
VCC
0V
0V
0V
~ –0.6V
~ 0.6V
–0.1V
0.1V
0.1V
DE
OUT
(DI = 0V)
OUT
(DI = VCC)
tPZH
tPZL
–0.1V
tPHZ
tPLZ
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUTY CYCLE;
tR, tF ≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
Figure 28. Driver Enable/Disable Times
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
200Mbps; 215 – 1PRBS.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
VA – VB
OR
VY – VZ
VA – VB
OR
VY – VZ
VCC
OUTPUT
INPUT
(PRBS)
0V
0.5VCC
tJ(PP)
0V
0V
0.5VCC
Figure 29. Driver Peak-to-Peak Jitter Characteristics


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn