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ADN4690E Datasheet(PDF) 15 Page - Analog Devices |
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ADN4690E Datasheet(HTML) 15 Page - Analog Devices |
15 / 20 page Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E Rev. A | Page 15 of 20 GLITCH-FREE POWER-UP/POWER-DOWN To minimize disruption to the bus when adding nodes, the M-LVDS outputs of the device are kept glitch-free when the device is powering up or down. This feature allows insertion of devices onto a live M-LVDS bus because the bus outputs are not switched on before the device is fully powered. In addition, all outputs are placed in a high impedance state when the device is powered off. FAULT CONDITIONS The ADN4691E/ADN4693E/ADN4696E/ADN4697E contain short-circuit current protection that protects the part under fault conditions in the case of short circuits on the bus. This protection limits the current in a fault condition to 24 mA at the transmitter outputs for short-circuit faults between −1 V and +3.4 V. Any network fault must be cleared to avoid data transmission errors and to ensure reliable operation of the data network and any devices that are connected to the network. RECEIVER INPUT THRESHOLDS/FAIL-SAFE Two receiver types are available, both of which incorporate protection against short circuits. The Type 1 receivers of the ADN4691E/ADN4693E incorporate 25 mV of hysteresis. This ensures that slow-changing signals or a loss of input does not result in oscillation of the receiver output. Type 1 receiver thresholds are ±50 mV; therefore, the state of the receiver output is indeterminate if the differential between A and B is about 0 V. This state occurs if the bus is idle (approximately 0 V on both A and B), with no drivers enabled on the attached nodes. Type 2 receivers (ADN4696E/ADN4697E) have an open circuit and bus-idle fail-safe. The input threshold is offset by 100 mV so that a logic low is present on the receiver output when the bus is idle or when the receiver inputs are open. The different receiver thresholds for the two receiver types are illustrated in Figure 36. See Table 12 and Table 13 for receiver output states under various conditions. TYPE 1 RECEIVER OUTPUT LOGIC 1 LOGIC 0 0.25 0.15 0.05 –0.05 –0.15 0 TYPE 2 RECEIVER OUTPUT LOGIC 1 LOGIC 0 UNDEFINED UNDEFINED Figure 36. Input Threshold Voltages |
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